Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74217 )
Change subject: mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmd
......................................................................
mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmd
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to
chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE`
config.
TEST=Able to build intel/mtlrvp with this code change.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Usha P <usha.p(a)intel.com>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
R src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Usha P: Looks good to me, approved
Eric Lai: Looks good to me, approved
Dinesh Gehlot: Looks good to me, approved
diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
similarity index 100%
rename from src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd
rename to src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
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Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/mainboard/google/skyrim/variants/markarth/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74087/comment/651f6452_60c79848
PS1, Line 15:
just to confirm, Markarth will force all type-c to gen1,or all usb3.0 ports?
as my understanding, there is one more sub3.0 type-A port
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74141 )
Change subject: soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
If this is fixed by each SoC, maybe use Kconfig?
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Hello Stefan Ott, build bot (Jenkins), Angel Pons, Arthur Heymans, Alexander Couzens, Swift Geek (Sebastian Grzywna),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74181
to look at the new patch set (#8).
Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
......................................................................
mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
mainboard_vbt_filename() used to assume that it is called after a call
to get_blc_pwm_freq_value() with a valid parameter, but currently it
is the first call of get_blc_pwm_freq_value(NULL), and will return 0,
so "data_led.vbt" is always returned, regardless of the actual type of
the panel.
Combined with the previous commit, in this commit
mainboard_vbt_filename() will explicitly read EDID string via
gm45_get_lvds_edid_str() and use this string to call
get_blc_pwm_freq_value().
Resolves: https://ticket.coreboot.org/issues/475
Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB
(CCFL).
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4
---
M src/mainboard/lenovo/x200/blc.c
1 file changed, 29 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74181/8
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Hello Stefan Ott, build bot (Jenkins), Angel Pons, Arthur Heymans, Alexander Couzens,
I'd like you to reexamine a change. Please visit
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Change subject: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz
......................................................................
mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz
Its EDID string is "LTN121AT07L02". The vendor sets BLC_PWM_CTL to
0x31313131.
This frequency seems working well on the x200 with this panel, which
is said to be LED.
Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
---
M src/mainboard/lenovo/x200/blc.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74182/11
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 )
Change subject: soc/intel/common: Order the different types of cores based on APIC IDs
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72132/comment/ef5614af_7d3ccda4
PS18, Line 13: /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
> Sorry to ask a stupid question, but isn't just the first list unordered? After ordering it, the assi […]
Hey, no problem, you can ask questions.
I chose the command output to indicate P-cores (for which hyper threading can be enabled) ordered first and E-cores ordered later as this can be seen visibly with thread_siblings_list output.
The APIC ID assignment to cores got changed from ADL to MTL. In ADL, APIC numbering for cores starts from P-cores (get lowers numbers) to E-Cores. But, APIC ID assignment got changed in MTL wherein E-cores get lower APIC IDs compare to P-cores. You may refer @section# 6.1 of doc#643504 for details.
Did I answer your query?
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Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173491):
https://review.coreboot.org/c/coreboot/+/74087/comment/66ffc9ba_8684de01
PS2, Line 9: From request, all type C port limit to to Gen1 5GHz.
Possible repeated word: 'to'
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Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: mb/google/rex: Enable audio BT offload
......................................................................
Patch Set 15:
(1 comment)
File src/mainboard/google/rex/variants/rex0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/72881/comment/ed8e9e16_788a68cb
PS15, Line 77: if (!fw_config_is_provisioned()) {
We can combine this into FW config probe. fw_config_probe will return false if provisioned, so you don't have to probe AUDIO_UNKNOWN as well. So we can do
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98363_CS42L42_SNDW))
else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))
else {
disable all
}
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Change subject: mb/google/rex: Add DTT thermal settings for thermal control
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71166/comment/d2fa47b1_b4695d42
PS6, Line 7: for policies
> What does “for policies” mean?
It's for thermal control.
https://review.coreboot.org/c/coreboot/+/71166/comment/b56261bb_04ee8ab4
PS6, Line 9: Add DTT thermal settings for policies for rex0 board
> Where are these values from?
Added information under commit message.
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