coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz
by Bill XIE (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Angel Pons, Arthur Heymans, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74182 to look at the new patch set (#9). Change subject: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz ...................................................................... mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz Its EDID string is "LTN121AT07L02". The vendor sets BLC_PWM_CTL to 0x31313131. This value seems working well on the x200 with this panel, which is said to be LED. Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74182/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Gerrit-Change-Number: 74182 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
by Dtrain Hsu (Code Review) 06 Apr '23

06 Apr '23

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74246 ) Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port ...................................................................... mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. BUG=b: BRANCH=firmware-brya-14505.B TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/74246/1 diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 2af7db4..6ba5ba0 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -336,6 +336,7 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "usb_lpm_incapable" = "true" device ref tcss_usb3_port3 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Gerrit-Change-Number: 74246 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
by Yu-Ping Wu (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74064 ) Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 6 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:52:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Add FW_CONFIG
by Eric Lai (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74102 ) Change subject: mb/google/myst: Add FW_CONFIG ...................................................................... Patch Set 21: (1 comment) File src/mainboard/google/myst/variants/myst/overridetree.cb: https://review.coreboot.org/c/coreboot/+/74102/comment/8885c3da_f3867762 PS4, Line 20: > So we don't need that to disable PCI or EMMC bus. Or some gpio need to update based on storage type. […] e.g. https://review.coreboot.org/c/coreboot/+/74133 , I see it uses CLKREQ, but fw config can work too. -- To view, visit https://review.coreboot.org/c/coreboot/+/74102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19 Gerrit-Change-Number: 74102 Gerrit-PatchSet: 21 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:52:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/mediatek/mt8188: Add GPIO driving functions
by Yu-Ping Wu (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74063 ) Change subject: soc/mediatek/mt8188: Add GPIO driving functions ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Gerrit-Change-Number: 74063 Gerrit-PatchSet: 6 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:51:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by Yu-Ping Wu (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74062 ) Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 3 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:50:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Reduce lastbus configuration size
by Yu-Ping Wu (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74061 ) Change subject: soc/mediatek/mt8188: Reduce lastbus configuration size ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Gerrit-Change-Number: 74061 Gerrit-PatchSet: 2 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:50:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by Jianeng Ceng (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Paul Menzel, Yidi Lin, cong yang. Jianeng Ceng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74115/comment/9274470a_999b2b38 PS12, Line 10: bonding the > These words can be moved to the previous line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 13 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 02:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by Jianeng Ceng (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Paul Menzel, Jianeng Ceng, Yidi Lin, cong yang. Hello build bot (Jenkins), jason-ch chen, Rex-BC Chen, Yu-Ping Wu, cong yang, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74115 to look at the new patch set (#13). Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel Geralt uses Samsung panel, and Mutto is responsible for bonding the panel and touch, so rename the panel description. Add power-on sequence for Samsung ATNA33XC20 panel. EDID Info: header: 00 ff ff ff ff ff ff 00 serial number: 4c 83 62 41 00 00 00 00 28 1e version: 01 04 basic params: b5 1d 11 78 02 chroma info: 0c f1 ae 52 3c b9 23 0c 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 2: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 3: 00 00 00 0f 00 d1 09 3c d1 09 3c 28 80 00 00 00 00 00 descriptor 4: 00 00 00 fe 00 41 54 4e 41 33 33 58 43 32 30 2d 30 20 extensions: 01 checksum: 6f BUG=b:276097739 TEST=test firmware display pass. Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 --- M src/mainboard/google/geralt/panel_geralt.c 1 file changed, 41 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/74115/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 13 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/skyrim: override Markarth PCIe config
by Eric Lai (Code Review) 06 Apr '23

06 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74133 ) Change subject: mb/google/skyrim: override Markarth PCIe config ...................................................................... mb/google/skyrim: override Markarth PCIe config Because Markarth PCIe port 1 use for eMMc not SD. So we need override PCIe config for Markarth. And also the Markarth have NVMe and eMMC SKU. Follow Winterhold to look at the NVMe CLKREQ signal before initializing the ports allowing us to identify which device is populated and only initialize that device. BRANCH=none BUG=b:275669215 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/variants/markarth/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/port_descriptors.c 3 files changed, 125 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index f44937b..1eb6926 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -126,6 +126,7 @@ config USE_VARIANT_DXIO_DESCRIPTOR bool default y if BOARD_GOOGLE_WINTERHOLD + default y if BOARD_GOOGLE_MARKARTH default n help Enable this to allow a variant to override the dxio descriptor values diff --git a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc index 83f7700..f9c705a 100644 --- a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./memory +romstage-y += port_descriptors.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c new file mode 100644 index 0000000..37edb02 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor emmc_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* eMMC */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, +}; + +static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_6, + .clk_req = CLK_REQ0, + }, +}; + +#define NVME_CLKREQ_GPIO 92 +void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) +{ + /* + * We can determine if a device is populated based on the state of the clkreq + * signal. If the device is present, the clkreq is held low by the device. If + * no device is present, clkreq is pulled high by an external pull-up. + * + * This allows checking the state of the NVMe device clkreq signal and enabling + * either eMMC or NVMe based on that. + */ + if (gpio_get(NVME_CLKREQ_GPIO)) { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling NVMe.\n"); + *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); + *dxio_descs = nvme_dxio_descriptors; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Gerrit-Change-Number: 74133 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit April 2023