coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74064 to look at the new patch set (#9). Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR ...................................................................... soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/spi.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74064/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 9 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: soc/mediatek/mt8188: Add GPIO driving functions
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74063 to look at the new patch set (#9). Change subject: soc/mediatek/mt8188: Add GPIO driving functions ...................................................................... soc/mediatek/mt8188: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/gpio.c 1 file changed, 265 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74063/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/74063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Gerrit-Change-Number: 74063 Gerrit-PatchSet: 9 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74062 to look at the new patch set (#6). Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... soc/mediatek/mt8186: Reduce GPIO code size in bootblock Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 122 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74062/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 6 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Juan Sanchez, Shelly Chang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... Patch Set 29: (1 comment) File src/mainboard/intel/archercity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/71968/comment/dd44cb5b_af2d0f9c PS27, Line 124: mupd->FspmConfig.serialDebugMsgLvl = 0x1; > Shouldn’t that be a Kconfig option. Hi Johnny/ Shelly, Could you add another patch to make this a kconfig option based on this example? https://review.coreboot.org/c/coreboot/+/65456 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 29 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Juan Sanchez Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 10:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Shelly Chang (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez. Shelly Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... Patch Set 29: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/a5065709_9afddbd1 PS28, Line 11: LiuxBoot > LinuxBoot Done File src/mainboard/intel/archercity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/71968/comment/3986a950_648dfab6 PS27, Line 83: mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; > wait I replied to wrong comment 😅 Done https://review.coreboot.org/c/coreboot/+/71968/comment/f8635459_bd0afb6c PS27, Line 96: "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); > It’s in the coding style, [section *Breaking long lines and strings*](https://doc.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 29 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Comment-Date: Thu, 06 Apr 2023 09:53:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
by Tony Huang (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74228 to look at the new patch set (#3). Change subject: mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts ...................................................................... mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assigna H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yaviks/memory/Makefile.inc M src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/74228/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389 Gerrit-Change-Number: 74228 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Shelly Chang (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Simon Chou, Johnny Lin, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez. Shelly Chang has uploaded a new patch set (#29) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... mb/intel: add Archer City CRB support Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 487 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 29 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by Yidi Lin (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen, Paul Menzel. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74062 ) Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74062/comment/dd402976_153c1bc9 PS5, Line 10: downloaded Sorry, it should be `downsized`. -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 09:44:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common: Order the different types of cores based on APIC IDs
by Ronak Kanabar (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Kyösti Mälkki, Jan Samek, Elyes Haouas. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 ) Change subject: soc/intel/common: Order the different types of cores based on APIC IDs ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 18 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 06 Apr 2023 09:33:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency
by Nico Huber (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Subrata Banik, Jérémy Compostella, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74141 ) Change subject: soc/intel/cmn/pcie: Allow SoC to overwrite snoop/no-snoop latency ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/pcie/pcie.c: https://review.coreboot.org/c/coreboot/+/74141/comment/44047722_164bd1c6 PS4, Line 14: __weak > > I could not find a document, but there are discussions on Gerrit. […] We usually use Kconfig for such overrides. Now that we have chipset devicetrees, a devicetree setting would also be possible (unless 0 is a valid value, then it would be inconvenient). In about 90% of the cases I see a weak function, it only seems handy because something else is already off. In this case even adding a function, not to mention a weak one, looks odd to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/74141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Gerrit-Change-Number: 74141 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 09:29:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023