coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: util/lint/stable-017: Update full config pattern matching
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel, Arthur Heymans. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74220 ) Change subject: util/lint/stable-017: Update full config pattern matching ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Gerrit-Change-Number: 74220 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 06 Apr 2023 12:32:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: SRIDHAR SIRICILLA, Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 17 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 12:28:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Felix Held (Code Review) 06 Apr '23

06 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... nb/intel/gm45: Export EDID-reading routine as a function It will cache decoded EDID string in a static array. If called more than once, a pointer to the static array is directly returned, without reading EDID again. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/74180 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 54 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index f28c6d1..c85a16c 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -447,6 +447,9 @@ u16 get_blc_pwm_freq_value(const char *edid_ascii_string); #include <device/device.h> +#include <edid.h> + +const char *gm45_get_lvds_edid_str(struct device *dev); struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8043822..6759e74 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -143,16 +143,46 @@ reg8)); } -static void gma_func0_init(struct device *dev) +const char *gm45_get_lvds_edid_str(struct device *dev) { u8 *mmio; u8 edid_data_lvds[128]; struct edid edid_lvds; + static char edid_str[EDID_ASCII_STRING_LENGTH + 1]; + + if (edid_str[0]) + return edid_str; + if (!gtt_res) + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res) + return NULL; + mmio = res2mmio(gtt_res, 0, 0); + + printk(BIOS_DEBUG, "LVDS EDID\n"); + intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, + edid_data_lvds, sizeof(edid_data_lvds)); + intel_gmbus_stop(mmio + GMBUS0); + + if (decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds) + != EDID_CONFORMANT) + return NULL; + memcpy(edid_str, edid_lvds.ascii_string, sizeof(edid_str)); + return edid_str; +} + +static void gma_func0_init(struct device *dev) +{ + u8 *mmio; const struct northbridge_intel_gm45_config *const conf = dev->chip_info; + const char *edid_str; intel_gma_init_igd_opregion(); - gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + edid_str = gm45_get_lvds_edid_str(dev); + if (!edid_str) + printk(BIOS_ERR, "Failed to obtain LVDS EDID string!\n"); + + /* gtt_res should have been inited in gm45_get_lvds_edid_str() */ if (!gtt_res) return; mmio = res2mmio(gtt_res, 0, 0); @@ -173,14 +203,8 @@ pci_dev_init(dev); } - printk(BIOS_DEBUG, "LVDS EDID\n"); - intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, - edid_data_lvds, sizeof(edid_data_lvds)); - intel_gmbus_stop(mmio + GMBUS0); - decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); - /* Post VBIOS init */ - gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); + gma_pm_init_post_vbios(dev, edid_str); if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/3b085fae_61aa0d68 PS3, Line 8: > > Please describe the problem, including what CAT means, and maybe a reference to the documentation […] I would directly write the whole thing (makes it easier to understand for me personally): "Detectable but Uncorrected Errors (DUE) can manifest themselves via blue screens or other system hangs/crashes. In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a three-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. Identifying the root cause of such events is notoriously difficult, as the system is effectively wedged and cannot be put into probe mode by JTAG-assisted hardware debuggers. In such extreme cases the machine check error handler at vector 0x18h does not execute correctly and no register information is captured." source: https://www.asset-intertech.com/resources/blog/2015/12/catastrophic-errors-… -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 12:20:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Michał Żygowski, Paul Menzel, Angel Pons, Krystian Hebel. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69870 ) Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/smm/Kconfig: https://review.coreboot.org/c/coreboot/+/69870/comment/37d8d3f3_5e1852ef PS4, Line 53: Intel Core processors select the periodic SMI rate via GEN_PMCON_A. > Maybe if the discrepancy was much higher, but for now only the apollolake has been identified with s […] You are right if its stays to being just one implementation there is no real difference in code size. But since your implementation in CB:68944 is really just changing one line depending on the Kconfig option, I find it easier to read. But I am fine with either implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/69870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11241836ecc9066d323977b030686567c87ed256 Gerrit-Change-Number: 69870 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 12:15:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74229 to look at the new patch set (#3). Change subject: mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB ...................................................................... mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB This patch updates the Rex flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/chromeos.fmd 1 file changed, 49 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74229/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout to meet WP_RO to 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74229 to look at the new patch set (#2). Change subject: mb/google/rex: Update Rex Flash Layout to meet WP_RO to 4MB ...................................................................... mb/google/rex: Update Rex Flash Layout to meet WP_RO to 4MB This patch updates the Rex flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/chromeos.fmd 1 file changed, 49 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74229/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74229 ) Change subject: mb/google/rex: Update Rex Flash Layout ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74229/comment/ce283eac_1c9a5a54 PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB. > Why is that done? what do you mean by this? we have product requirement to create 4MB WP_RO hence, we have done that. https://review.coreboot.org/c/coreboot/+/74229/comment/20ef5cb5_3fd4e49e PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB. : : Changes for chromeos.fmd: : : SI_BIOS: : RW_SECTION_A/B: Reduce to 7MB. : RW_LEGACY: Reduce to 1MB. : RW_MISC: Increased to 1MB. : RW_UNUSED: 3MB (reserved) : WP_RO: Reduce to 4MB : : Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the : SPI Flash. > Why not make it two (or three) commits? the goal is to reduce WP_RO to 4MB hence, in that process what all adjustment we need to do it has to be done at one shot else system will not boot. Honestly I think these comments are not taking us anywhere. I' feeling supervised while submitting the code. I'm not feeling this is like any code review. File src/mainboard/google/rex/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74229/comment/c990a26d_7bd9457b PS1, Line 7: 7M > I’d make these non-functional changes a separate commit. I don't agree with this. This CL attempts to make WP_RO to 4MB hence, all relevant changes are here. -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 12:05:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, Paul Menzel. jason-ch chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74064 ) Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74064/comment/46f6fa9d_f5278cd5 PS9, Line 15: TEST=build pass > And apparently boot? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 10 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 11:46:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2023