coreboot-gerrit April 2023

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[M] Change in coreboot[master]: Documentation/mainboard/hp/compaq_8200_sff.md: Add more information a...
by build bot (Jenkins) (Code Review) 06 Apr '23

06 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74248 ) Change subject: Documentation/mainboard/hp/compaq_8200_sff.md: Add more information about internal flashing ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173524): https://review.coreboot.org/c/coreboot/+/74248/comment/dbfca8d0_f3bf1c1a PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173524): https://review.coreboot.org/c/coreboot/+/74248/comment/6fb6f53e_0a080b37 PS1, Line 9: Add a more detailed explanation of internal flashing on the HP Compaq 8200 Elite SFF. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 Gerrit-Change-Number: 74248 Gerrit-PatchSet: 1 Gerrit-Owner: Václav Straka Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:10:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/mainboard/hp/compaq_8200_sff.md: Add more information a...
by Václav Straka (Code Review) 06 Apr '23

06 Apr '23

Václav Straka has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74248 ) Change subject: Documentation/mainboard/hp/compaq_8200_sff.md: Add more information about internal flashing ...................................................................... Documentation/mainboard/hp/compaq_8200_sff.md: Add more information about internal flashing Add a more detailed explanation of internal flashing on the HP Compaq 8200 Elite SFF. Signed-off-by: Vesek <venda.straka(a)gmail.com> Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 --- M Documentation/mainboard/hp/compaq_8200_sff.md A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg 2 files changed, 147 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/1 diff --git a/Documentation/mainboard/hp/compaq_8200_sff.md b/Documentation/mainboard/hp/compaq_8200_sff.md index 3e83e25..bf157d8 100644 --- a/Documentation/mainboard/hp/compaq_8200_sff.md +++ b/Documentation/mainboard/hp/compaq_8200_sff.md @@ -1,80 +1,135 @@ -# HP Compaq 8200 Elite SFF - -This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop -from [HP]. - -## TODO - -The following things are still missing from this coreboot port: - -- Extended HWM reporting -- Advanced LED control -- Advanced power configuration in S3 - -## Flashing coreboot - -```eval_rst -+---------------------+------------+ -| Type | Value | -+=====================+============+ -| Socketed flash | no | -+---------------------+------------+ -| Model | MX25L6406E | -+---------------------+------------+ -| Size | 8 MiB | -+---------------------+------------+ -| In circuit flashing | yes | -+---------------------+------------+ -| Package | SOIC-8 | -+---------------------+------------+ -| Write protection | No | -+---------------------+------------+ -| Dual BIOS feature | No | -+---------------------+------------+ -| Internal flashing | yes | -+---------------------+------------+ -``` - -### Internal programming - -The SPI flash can be accessed using [flashrom]. - -### External programming - -External programming with an SPI adapter and [flashrom] does work, but it powers the -whole southbridge complex. You need to supply enough current through the programming adapter. - -If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, -as otherwise there's not enough space near the flash. - -**Position of SOIC-8 flash IC near 2nd DIMM holder** -![][compaq_8200_flash1] - -[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg - -**Closeup view of SOIC-8 flash IC** -![][compaq_8200_flash2] - -[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg - -## Technology - -```eval_rst -+------------------+--------------------------------------------------+ -| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | -+------------------+--------------------------------------------------+ -| Southbridge | bd82x6x | -+------------------+--------------------------------------------------+ -| CPU | model_206ax | -+------------------+--------------------------------------------------+ -| SuperIO | :doc:`../../superio/nuvoton/npcd378` | -+------------------+--------------------------------------------------+ -| EC | | -+------------------+--------------------------------------------------+ -| Coprocessor | Intel ME | -+------------------+--------------------------------------------------+ -``` - -[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707 -[HP]: https://www.hp.com/ -[flashrom]: https://flashrom.org/Flashrom +# HP Compaq 8200 Elite SFF + +This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop +from [HP]. + +## TODO + +The following things are still missing from this coreboot port: + +- Extended HWM reporting +- Advanced LED control +- Advanced power configuration in S3 + +## Flashing coreboot + +```eval_rst ++---------------------+-------------------------+ +| Type | Value | ++=====================+=========================+ +| Socketed flash | no | ++---------------------+-------------------------+ +| Model | MX25L6406E/MX25L6408E | ++---------------------+-------------------------+ +| Size | 8 MiB | ++---------------------+-------------------------+ +| In circuit flashing | yes | ++---------------------+-------------------------+ +| Package | SOIC-8 | ++---------------------+-------------------------+ +| Write protection | bios region | ++---------------------+-------------------------+ +| Dual BIOS feature | No | ++---------------------+-------------------------+ +| Internal flashing | yes | ++---------------------+-------------------------+ +``` +### Flash layout +The original layout of the flash should look like this: +``` +00000000:00000fff fd +00510000:007fffff bios +00003000:0050ffff me +00001000:00002fff gbe +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. +``` +flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom +``` +After shorting the FDO jumper you gain access to the full flash but you +still cannot write in the bios region. + +**Position of FDO jumper close to the IO and second fan connector** + +![][compaq_8200_jumper] + +[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg + +You can use a modified [IFD Hack] originally used on MacBooks, you will +need to read both guides. + +Since you can still write in the flash descriptor region you can shrink +the ME and then move the bios region into where the ME originaly was. +Coreboot does not by default restrict writing to any part of the flash so +you will first flash a small coreboot build and after it boots, flash +the full one. + +The temporary flash layout with the ME shrinked should look like this: +``` +00000000:00000fff fd +00023000:001fffff bios +00003000:00022fff me +00001000:00002fff gbe +00200000:007fffff pd +``` +It is very important to use these exact numbers or you will get a brick, +but you should be already familiar with the risks if you got so far. +The temporary flash size to set in coreboot is 2 MB, and you can fill +the rest with zeros to get the matching size using: +``` +dd if=/dev/zero of=6M.bin bs=1024 count=6144 +cat coreboot.rom 6M.bin > coreboot8.rom +``` + +The final flash layout after you already have the temporary coreboot +installation running should look like this: +``` +00000000:00000fff fd +00023000:007fffff bios +00003000:00022fff me +00001000:00002fff gbe +``` +More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md). +### External programming + +External programming with an SPI adapter and [flashrom] does work, but it powers the +whole southbridge complex. You need to supply enough current through the programming adapter. + +If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, +as otherwise there's not enough space near the flash. + +**Position of SOIC-8 flash IC near 2nd DIMM holder** +![][compaq_8200_flash1] + +[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg + +**Closeup view of SOIC-8 flash IC** +![][compaq_8200_flash2] + +[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | :doc:`../../superio/nuvoton/npcd378` | ++------------------+--------------------------------------------------+ +| EC | | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/3877… +[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707 +[HP]: https://www.hp.com/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg b/Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg new file mode 100644 index 0000000..ba30746 --- /dev/null +++ b/Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/74248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 Gerrit-Change-Number: 74248 Gerrit-PatchSet: 1 Gerrit-Owner: Václav Straka Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: payloads/external/edk2: Add option to clone edk2-platforms repo
by Felix Held (Code Review) 06 Apr '23

06 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68872 ) Change subject: payloads/external/edk2: Add option to clone edk2-platforms repo ...................................................................... payloads/external/edk2: Add option to clone edk2-platforms repo Add possibility to clone edk2-platforms repository. Some edk2 repositories may use modules from edk2-platforms which contains various feature packages for Intel platforms, e.g VT-d driver if DMA protection is enabled. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68872 Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/external/Makefile.inc M payloads/external/edk2/Kconfig M payloads/external/edk2/Makefile 3 files changed, 79 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 91fce58..475427e 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -166,6 +166,9 @@ CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \ CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \ CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \ + CONFIG_EDK2_USE_EDK2_PLATFORMS=$(CONFIG_EDK2_USE_EDK2_PLATFORMS) \ + CONFIG_EDK2_PLATFORMS_REPOSITORY=$(CONFIG_EDK2_PLATFORMS_REPOSITORY) \ + CONFIG_EDK2_PLATFORMS_TAG_OR_REV=$(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) \ CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \ CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \ CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \ diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 454aef0..e3bb157 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -61,6 +61,30 @@ EDK2_REPOSITORY, and in the case of a branch name, prefixed with origin i.e. "origin/uefipayload_202202" +config EDK2_USE_EDK2_PLATFORMS + bool "Use edk2-platforms repository" + default n + help + Clone edk2-platforms repository to the edk2 workspace for additional modules. + +if EDK2_USE_EDK2_PLATFORMS + +config EDK2_PLATFORMS_REPOSITORY + string "URL to git repository for edk2-platforms" + default "https://github.com/tianocore/edk2-platforms" + help + URL to the edk2-platfors repository to clone. + +config EDK2_PLATFORMS_TAG_OR_REV + string "Insert a commit's SHA-1 or a branch name" + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. This must exist in + EDK2_PLATFORMS_REPOSITORY, and in the case of a branch name, prefixed with + origin i.e. "origin/master" + +endif + choice prompt "edk2 build" default EDK2_RELEASE diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 27ce4a9..b241cf9 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -6,7 +6,22 @@ project_name = edk2 export WORKSPACE := $(CURDIR)/workspace export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY))) + +ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y) +export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms +export PACKAGES_PATH := $(EDK2_PATH):\ + $(EDK2_PLATFORMS_PATH)/Platform/Intel:\ + $(EDK2_PLATFORMS_PATH)/Silicon/Intel:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/Debugging:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/Network:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/OutOfBandManagement:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/PowerManagement:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/SystemInformation:\ + $(EDK2_PLATFORMS_PATH)/Features/Intel/UserInterface +else export PACKAGES_PATH := $(EDK2_PATH) +endif OBJCOPY = $(GCC_PREFIX)objcopy @@ -119,6 +134,23 @@ $(WORKSPACE): mkdir $(WORKSPACE) +$(EDK2_PLATFORMS_PATH): $(WORKSPACE) + if [ ! -d "$(EDK2_PLATFORMS_PATH)" ]; then \ + git clone --recurse-submodules $(CONFIG_EDK2_PLATFORMS_REPOSITORY) $(EDK2_PLATFORMS_PATH) -j5; \ + fi + cd $(EDK2_PLATFORMS_PATH); \ + if ! git rev-parse --verify -q $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) >/dev/null; then \ + echo " $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) is not a valid git reference"; \ + exit 1; \ + fi; \ + if git status --ignore-submodules=dirty | grep -q "nothing to commit, working tree clean"; then \ + echo " Checking out edk2-platforms revision $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV)"; \ + git checkout --detach $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) -f; \ + else \ + echo " Working directory not clean; will not overwrite"; \ + fi; \ + git submodule update --init --checkout + $(EDK2_PATH): $(WORKSPACE) if [ ! -d "$(EDK2_PATH)" ]; then \ git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ @@ -176,6 +208,7 @@ echo " ##### $(project_name) Build Summary #####" echo " Repository: $(CONFIG_EDK2_REPOSITORY)" echo " Branch: $(CONFIG_EDK2_TAG_OR_REV)" + echo " Packages path: $(PACKAGES_PATH)" echo " $(BUILD_STR)" | \ sed -e 's/--/-/g' -e 's/-/\n /g' | sort | sed \ -e 's/a /Architecture: /g' \ @@ -187,7 +220,7 @@ -e 's/s /Build: Silent/' \ -e 's/t /Toolchain: /' -prep: $(EDK2_PATH) clean checktools logo +prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \ -- To view, visit https://review.coreboot.org/c/coreboot/+/68872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9 Gerrit-Change-Number: 68872 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/amd/birman: Enable PCIe RTD3 support
by Fred Reitberger (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74247 ) Change subject: mb/amd/birman: Enable PCIe RTD3 support ...................................................................... mb/amd/birman: Enable PCIe RTD3 support Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/devicetree_phoenix.cb 2 files changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/74247/1 diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index 7fa541c..3d0ec61 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -8,6 +8,7 @@ select EC_ACPI select SOC_AMD_COMMON_BLOCK_USE_ESPI if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select AMD_SOC_CONSOLE_UART if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD + select DRIVERS_PCIE_RTD3_DEVICE select MAINBOARD_HAS_CHROMEOS select PCIEXP_ASPM select PCIEXP_CLK_PM diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index ff54e1f..2fc78aa 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -162,12 +162,24 @@ device domain 0 on device ref iommu on end device ref gpp_bridge_1_1 on end # MXM - device ref gpp_bridge_1_2 on end # NVMe SSD1 + device ref gpp_bridge_1_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD1 device ref gpp_bridge_1_3 on end # GBE device ref gpp_bridge_2_1 on end # SD device ref gpp_bridge_2_2 on end # WWAN device ref gpp_bridge_2_3 on end # WIFI - device ref gpp_bridge_2_4 on end # NVMe SSD0 + device ref gpp_bridge_2_4 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD0 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) -- To view, visit https://review.coreboot.org/c/coreboot/+/74247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3 Gerrit-Change-Number: 74247 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman
by Fred Reitberger (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Jason Glenesk, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69705 to look at the new patch set (#12). Change subject: mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman ...................................................................... mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B v0.7 Update devicetree to reference the updated DXIO descriptors. TEST=boot birman and note the devices show up in the logs correctly Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/birman/port_descriptors_phoenix.c 2 files changed, 187 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69705/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 12 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB
by Paul Menzel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74229 ) Change subject: mb/google/rex: Update Rex Flash Layout to fit WP_RO within 4MB ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74229/comment/7f934193_14de6de9 PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB. > > Why is that done? […] The board was apparently added with 8 MB, so why is it too big now? What optimization is done? https://review.coreboot.org/c/coreboot/+/74229/comment/ee97b93f_f6c87c7f PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB. : : Changes for chromeos.fmd: : : SI_BIOS: : RW_SECTION_A/B: Reduce to 7MB. : RW_LEGACY: Reduce to 1MB. : RW_MISC: Increased to 1MB. : RW_UNUSED: 3MB (reserved) : WP_RO: Reduce to 4MB : : Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the : SPI Flash. > > Why not make it two (or three) commits? […] I am sorry you are feeling this way. File src/mainboard/google/rex/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74229/comment/08c7718a_efc8cf20 PS1, Line 7: 7M > > > I’d make these non-functional changes a separate commit. […] Changing 7092K to 7M is cosmetic, isn’t it? -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 13:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/cmn/cse: Handle EOP completion asynchronously
by Tarun Tuli (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74214 ) Change subject: soc/intel/cmn/cse: Handle EOP completion asynchronously ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Gerrit-Change-Number: 74214 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 13:20:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Fred Reitberger (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 10 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 13:16:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Ivy Jian, Maximilian Brune, Angel Pons, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/40e1f163_aed1b321 PS3, Line 8: > I would directly write the whole thing (makes it easier to understand for me personally): > "Detectable but Uncorrected Errors (DUE) can manifest themselves via blue screens or other system hangs/crashes. In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a three-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. Identifying the root cause of such events is notoriously difficult, as the system is effectively wedged and cannot be put into probe mode by JTAG-assisted hardware debuggers. In such extreme cases the machine check error handler at vector 0x18h does not execute correctly and no register information is captured." > source: https://www.asset-intertech.com/resources/blog/2015/12/catastrophic-errors-… Sorry! I don't understand what is the point of adding those details? I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. I'm intended to enable a bit which is described in the EDS. I don't think for enabling the bit related to 3-strike, I need to write whole paragraph about what is 3-strike error. I have wrote the commit msg to explain what this patch does ``` This patch prevents the Three Strike Counter from incrementing, which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. ``` If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 13:13:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz
by Bill XIE (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Stefan Ott, Angel Pons, Alexander Couzens. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74182 ) Change subject: mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750Hz ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74182/comment/7eeb3339_7c7b86eb PS8, Line 7: LTN121AT07L02 > nit: Looks like the actual panel model is `LTN121AT07-L02` with a hyphen. The EDID string is "LTN121AT07L02". Both are now recorded in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/74182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Gerrit-Change-Number: 74182 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 06 Apr 2023 13:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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