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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
......................................................................
soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.8 and 5.19 in MT8188
Functional Specification.
BUG=b:270911452
TEST=boot with following logs
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b
Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/spi.c
1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74064/10
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I'd like you to reexamine a change. Please visit
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Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
util/inteltool: Add support for Jasper Lake
Tested on: GW-R86S-P1
Documents: Intel Datasheet: 634545, rev. 001
Document Number: Intel Pentium Silver and Intel
Celeron Processor Datasheet, vol. 2 of 2
Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/jasperlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 697 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/17
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Change subject: cpu/smm_module_loader.c: Fix up CPU index locally
......................................................................
Patch Set 30:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64802/comment/adbb7a3e_a63cb590
PS30, Line 11: an Intel
: platform
> Which one did you test with?
This is a TEST statement on how to test whether this works. This isn't a statement about it being tested on any Intel platform even though it was at some point.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 )
Change subject: mb/intel: add Archer City CRB support
......................................................................
Patch Set 29:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71968/comment/2cced1b9_18128498
PS29, Line 7: add Archer City CRB support
Maybe mention the type: Add 2 SPR sockets CRB Archer City
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Change subject: util/lint/stable-017: Update full config pattern matching
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74220/comment/b6ef0a20_7162003c
PS2, Line 9: CONFIG_ARCH gives false positives for CONFIG_USE_EXP_X86_64_SUPPORT so
: use a different string: 'CONFIG_MAINBOARD_DIR'.
> I don't understand. How does CONFIG_USE_EXP_X86_64_SUPPORT influence the grep for CONFIG_ARCH_? I only see that CONFIG_USE_EXP_X86_64_SUPPORT selects ARCH_ALL_STAGES_X86_64.
> ARCH_ALL_STAGES_X86_64 is not a configurable option, so that is apparently also not the issue.
> I tried it out and there also seems to be no problem with the current configs directory.
Sorry wrong config option. Fixed
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I'd like you to reexamine a change. Please visit
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Change subject: util/lint/stable-017: Update full config pattern matching
......................................................................
util/lint/stable-017: Update full config pattern matching
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so
use a different string: 'CONFIG_MAINBOARD_DIR'.
Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/lint/lint-stable-017-configs
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/74220/3
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Change subject: cpu/smm_module_loader.c: Fix up CPU index locally
......................................................................
Patch Set 30:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64802/comment/83a4294f_e2f0d986
PS30, Line 11: an Intel
: platform
Which one did you test with?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74229 )
Change subject: mb/google/rex: Update Rex Flash Layout
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74229/comment/179403b7_a0512033
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
Why is that done?
https://review.coreboot.org/c/coreboot/+/74229/comment/5cee9331_96a5af93
PS1, Line 9: This patch updates the Rex flash layout to optimize WP_RO to 4MB.
:
: Changes for chromeos.fmd:
:
: SI_BIOS:
: RW_SECTION_A/B: Reduce to 7MB.
: RW_LEGACY: Reduce to 1MB.
: RW_MISC: Increased to 1MB.
: RW_UNUSED: 3MB (reserved)
: WP_RO: Reduce to 4MB
:
: Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
: SPI Flash.
Why not make it two (or three) commits?
File src/mainboard/google/rex/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/74229/comment/de15407f_f9bd2f6d
PS1, Line 7: 7M
I’d make these non-functional changes a separate commit.
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Patrick Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74133 )
Change subject: mb/google/skyrim: override Markarth PCIe config
......................................................................
Patch Set 5: Code-Review+1
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