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Change subject: util/lint/stable-017: Update full config pattern matching
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74220/comment/8f637385_ab0530ba
PS2, Line 9: CONFIG_ARCH gives false positives for CONFIG_USE_EXP_X86_64_SUPPORT so
: use a different string: 'CONFIG_MAINBOARD_DIR'.
I don't understand. How does CONFIG_USE_EXP_X86_64_SUPPORT influence the grep for CONFIG_ARCH_? I only see that CONFIG_USE_EXP_X86_64_SUPPORT selects ARCH_ALL_STAGES_X86_64.
ARCH_ALL_STAGES_X86_64 is not a configurable option, so that is apparently also not the issue.
I tried it out and there also seems to be no problem with the current configs directory.
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Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
Patch Set 15: Code-Review+1
(6 comments)
Patchset:
PS15:
All of my comments are resolved now
File util/inteltool/gpio_names/jasperlake.h:
https://review.coreboot.org/c/coreboot/+/73934/comment/74a222e4_0f7adef7
PS12, Line 539: // Deep Sleep Well group
> What was done? I see no change here. […]
Done
https://review.coreboot.org/c/coreboot/+/73934/comment/5bacd97d_f8c16d7a
PS12, Line 553: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL",
> ... […]
Done
https://review.coreboot.org/c/coreboot/+/73934/comment/f4803773_525320c1
PS12, Line 584:
> I'm not against adding comments. […]
Done
https://review.coreboot.org/c/coreboot/+/73934/comment/88650a6c_e5c0325c
PS12, Line 657: &jasperlake_pch_group_b,
> Done
Done
https://review.coreboot.org/c/coreboot/+/73934/comment/a906a149_11a4297e
PS12, Line 660:
> Done
Done
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Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#16).
Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
util/inteltool: Add support for Jasper Lake
Tested on: GW-R86S-P1
Documents: Intel Datasheet: 634545, rev. 001
Document Number: Intel Pentium Silver and Intel
Celeron Processor Datasheet, vol. 2 of 2
Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/jasperlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 694 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/16
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Change subject: cpu/x86/mp_init.c: Generate a C header to get start32 offset
......................................................................
Patch Set 30: Code-Review+1
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74229 )
Change subject: mb/google/rex: Update Rex Flash Layout
......................................................................
mb/google/rex: Update Rex Flash Layout
This patch updates the Rex flash layout to optimize WP_RO to 4MB.
Changes for chromeos.fmd:
SI_BIOS:
RW_SECTION_A/B: Reduce to 7MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Increased to 1MB.
RW_UNUSED: 3MB (reserved)
WP_RO: Reduce to 4MB
Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.
BUG=b:277143384
TEST=Able to build and boot google/rex with FSP release and debug image.
Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/chromeos.fmd
1 file changed, 49 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74229/1
diff --git a/src/mainboard/google/rex/chromeos.fmd b/src/mainboard/google/rex/chromeos.fmd
index 3521232..b2c0e84 100644
--- a/src/mainboard/google/rex/chromeos.fmd
+++ b/src/mainboard/google/rex/chromeos.fmd
@@ -4,38 +4,45 @@
SI_ME
}
SI_BIOS 23M {
- RW_SECTION_A 7092K {
+ RW_SECTION_A 7M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 4400K
}
- RW_MISC 152K {
- RW_ELOG(PRESERVE) 4K
- RW_SHARED 4K {
- SHARED_DATA 4K
- }
- RW_VPD(PRESERVE) 8K
- RW_NVRAM(PRESERVE) 8K
- UNIFIED_MRC_CACHE(PRESERVE) 128K {
- RECOVERY_MRC_CACHE 64K
- RW_MRC_CACHE 64K
- }
- }
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
- RW_SECTION_B 7092K {
+ RW_SECTION_B 7M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 4400K
}
+ RW_MISC 1M {
+ UNIFIED_MRC_CACHE(PRESERVE) 128K {
+ RECOVERY_MRC_CACHE 64K
+ RW_MRC_CACHE 64K
+ }
+ RW_ELOG(PRESERVE) 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+ # It is placed in the common `chromeos.fmd` file because it is only 4K and there
+ # is free space in the RW_MISC region that cannot be easily reclaimed because
+ # the RW_SECTION_B must start on the 16M boundary.
+ RW_SPD_CACHE(PRESERVE) 4K
+ RW_VPD(PRESERVE) 8K
+ RW_NVRAM(PRESERVE) 24K
+ }
RW_LEGACY(CBFS) 1M
+ RW_UNUSED 3M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
- WP_RO 8M {
+ WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_GSCVD 8K
RO_SECTION {
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Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: util/inteltool: Add support for Jasper Lake
......................................................................
util/inteltool: Add support for Jasper Lake
Tested on: GW-R86S-P1
Documents: Intel Datasheet: 634545, rev. 001
Document Number: Intel Pentium Silver and Intel
Celeron Processor Datasheet, vol. 2 of 2
Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d
Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/jasperlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 694 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/15
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Change subject: soc/mediatek/mt8186: Move GPIO driving-related functions to common
......................................................................
soc/mediatek/mt8186: Move GPIO driving-related functions to common
Move GPIO driving-related functions to common for code reuse.
BUG=b:270911452
TEST=build pass
Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c
Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com>
---
M src/soc/mediatek/common/gpio.c
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
M src/soc/mediatek/mt8188/include/soc/gpio.h
5 files changed, 138 insertions(+), 131 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74068/6
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