Attention is currently required from: Tarun Tuli.
Hello build bot (Jenkins), Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74228
to look at the new patch set (#2).
Change subject: mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
......................................................................
mb/google/nissa/var/yaviks: Generate SPD ID for new memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assigna
H58G66AK6BX070 4 (0100)
H58G66BK7BX067 5 (0101)
MT62F2G32D4DS-026 WT:B 5 (0101)
K3KL9L90CM-MGCT 5 (0101)
BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/yaviks/memory/Makefile.inc
M src/mainboard/google/brya/variants/yaviks/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/yaviks/memory/mem_parts_used.txt
3 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/74228/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 )
Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/ibm/sbp1/Kconfig:
https://review.coreboot.org/c/coreboot/+/73392/comment/0ec3c79f_f150b1ff
PS9, Line 31: MAX_SOCKET_UPD
> I don't understand the question. […]
Why are there two Kconfigs?
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74185 )
Change subject: soc/intel/xeon_sp/spr: Drop devicetree setting X2apic
......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8
PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG
and payload TianoCore : https://lava.9esec.io/r/157782
PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG
and payload SeaBIOS : https://lava.9esec.io/r/157781
PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35
and payload TianoCore : https://lava.9esec.io/r/157780
PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35
and payload SeaBIOS : https://lava.9esec.io/r/157779
PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64
and payload SeaBIOS : https://lava.9esec.io/r/157778
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN
and payload SeaBIOS : https://lava.9esec.io/r/157777
PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_
and payload SeaBIOS : https://lava.9esec.io/r/157776
FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX
and payload SeaBIOS : https://lava.9esec.io/r/157775
Please note: This test is under development and might not be accurate at all!
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jason-ch chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74064 )
Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74064/comment/c61bf225_a82366fe
PS6, Line 10:
> What drive strength was used before this change?
Typically, the default driving is 2 mA.
https://review.coreboot.org/c/coreboot/+/74064/comment/543e2edb_096c8816
PS6, Line 15: TEST=build pass
> If you run it, please paste the new debug messages.
Done
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Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74209 )
Change subject: soc/intel/cmn/block/cse: Implement an API to get ISH version
......................................................................
Patch Set 5:
(3 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/1758c942_b22a0b81
PS4, Line 1216: /*
: * This API can only be executed after FSP-M has been initialized. This is because the
: * command relies on resources that are not available until CSE DRAM initialization
: * command has been sent.
: */
> Give one space to start with, here is some sample style which u can follow. […]
Ack
https://review.coreboot.org/c/coreboot/+/74209/comment/bf567737_bcd32def
PS4, Line 1221: #if ENV_RAMSTAGE
> keep everything inside same #if ENV_RAMSTAGE at line 1267
Ack
https://review.coreboot.org/c/coreboot/+/74209/comment/5722f71f_19d0ed20
PS4, Line 1227: sizeof(struct fw_version)
> use directly in line #1229
Ack
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Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74062/comment/4b139bb5_926b1a24
PS3, Line 2: jason-ch chen
> Is your name written jason-ch? You could also use a capital first letter.
Done
https://review.coreboot.org/c/coreboot/+/74062/comment/cc69ed23_1019d5e0
PS3, Line 8:
> Please describe the problem, and mention the sizes before and after.
Done
https://review.coreboot.org/c/coreboot/+/74062/comment/1d5efbc3_bebb25d1
PS3, Line 13: jason-ch chen
> Ditto.
Done
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74068
to look at the new patch set (#4).
Change subject: soc/mediatek/mt8186: Move GPIO driving-related functions to common
......................................................................
soc/mediatek/mt8186: Move GPIO driving-related functions to common
Move GPIO driving-related functions to common for code reuse.
BUG=b:270911452
TEST=build pass
Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c
Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com>
---
M src/soc/mediatek/common/gpio.c
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
M src/soc/mediatek/mt8188/include/soc/gpio.h
5 files changed, 138 insertions(+), 131 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74068/4
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