coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX
by Fred Reitberger (Code Review) 06 Apr '23

06 Apr '23

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74249 ) Change subject: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX ...................................................................... soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX The phoenix SoC does not support multiple EFS locations. Set the default to the only valid value and prevent mainboard overrides. TEST=build birman-phoenix Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 --- M src/soc/amd/phoenix/Kconfig 1 file changed, 17 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/74249/1 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 5d3adec..6c24933 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -303,14 +303,9 @@ menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" + int range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help Typically this is calculated by the ROM size, but there may be situations where you want to put the firmware directory -- To view, visit https://review.coreboot.org/c/coreboot/+/74249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Gerrit-Change-Number: 74249 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPU power sequencing to add Had...
by Tarun Tuli (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Subrata Banik, Kapil Porwal, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73896 ) Change subject: mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support ...................................................................... Patch Set 20: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/73896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Gerrit-Change-Number: 73896 Gerrit-PatchSet: 20 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:41:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/ibm: Add 4 SPR sockets server board IBM SBP1
by Jonathan Zhang (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, David Hendricks, Angel Pons, Shuo Liu, Nill Ge. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1 ...................................................................... Patch Set 10: (1 comment) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/e7bcd283_592f586c PS9, Line 31: MAX_SOCKET_UPD > The soc code has two Kconfigs. Please refer to the soc code authors for design related questions. MAX_SOCKET_UPD matches with how the FSP was built. MAX_SOCKET is the maximum number of sockets supported by a mainboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/xeon_sp/acpi: Fix _OSC method
by Jonathan Zhang (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Ziang Wang, Christian Walter, Arthur Heymans, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74231 ) Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Gerrit-Change-Number: 74231 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:30:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
by build bot (Jenkins) (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Kapil Porwal, Usha P. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74254 ) Change subject: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173536): https://review.coreboot.org/c/coreboot/+/74254/comment/50c5aa66_2952fffa PS1, Line 9: This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173536): https://review.coreboot.org/c/coreboot/+/74254/comment/097dd13f_65941de0 PS1, Line 24: TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Gerrit-Change-Number: 74254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:29:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
by build bot (Jenkins) (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Kapil Porwal, Usha P. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74252 ) Change subject: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173534): https://review.coreboot.org/c/coreboot/+/74252/comment/0ad7df16_8f1e7afd PS1, Line 23: BUG=b:277143384 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Gerrit-Change-Number: 74252 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 14:28:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74254 ) Change subject: mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB ...................................................................... mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd --- M src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd 1 file changed, 51 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/74254/1 diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd index bd250f5f..6ca1cc6 100644 --- a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd @@ -4,39 +4,47 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7604K { + RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7604K { + RW_SECTION_B 7680K { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K - RO_GSCVD 8K + RO_SECTION { FMAP 2K RO_FRID 64 -- To view, visit https://review.coreboot.org/c/coreboot/+/74254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Gerrit-Change-Number: 74254 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74253 ) Change subject: mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB ...................................................................... mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MB This patch updates the Rex debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae --- M src/mainboard/google/rex/chromeos-debug-fsp.fmd 1 file changed, 50 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/74253/1 diff --git a/src/mainboard/google/rex/chromeos-debug-fsp.fmd b/src/mainboard/google/rex/chromeos-debug-fsp.fmd index bd250f5f..c3c1336 100644 --- a/src/mainboard/google/rex/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/rex/chromeos-debug-fsp.fmd @@ -4,37 +4,45 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7604K { + RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - UNIFIED_MRC_CACHE(PRESERVE) 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7604K { + RW_SECTION_B 7680K { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_GSCVD 8K RO_SECTION { -- To view, visit https://review.coreboot.org/c/coreboot/+/74253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae Gerrit-Change-Number: 74253 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74252 ) Change subject: mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB ...................................................................... mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MB This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 53 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/74252/1 diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index 22dbff5..a5bc538 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -4,34 +4,45 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7092K { + RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 ME_RW_A(CBFS) 4400K } - RW_MISC 152K { - UNIFIED_MRC_CACHE 128K { - RECOVERY_MRC_CACHE 64K - RW_MRC_CACHE 64K - } - RW_ELOG(PRESERVE) 4K - RW_SHARED 4K { - SHARED_DATA 4K - } - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 8K - } - RW_SECTION_B 7092K { + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 ME_RW_B(CBFS) 4400K } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for rex variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } RW_LEGACY(CBFS) 1M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO 8M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K -- To view, visit https://review.coreboot.org/c/coreboot/+/74252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Gerrit-Change-Number: 74252 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74229 to look at the new patch set (#4). Change subject: mb/google/rex: Update Flash Layout to fit WP_RO within 4MB ...................................................................... mb/google/rex: Update Flash Layout to fit WP_RO within 4MB This patch updates the Rex flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/chromeos.fmd 1 file changed, 49 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/74229/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Gerrit-Change-Number: 74229 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023