coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64342 ) ( 24 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path ...................................................................... cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/cpu.c M src/cpu/x86/mp_init.c M src/device/cpu_device.c M src/include/cpu/cpu.h M src/include/device/path.h 5 files changed, 30 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index b0227c2..60b236c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -211,24 +211,6 @@ cpu->ops = driver ? driver->ops : NULL; } -/* Keep track of default APIC ids for SMM. */ -static int cpus_default_apic_id[CONFIG_MAX_CPUS]; - -/* Function to keep track of cpu default apic_id */ -void cpu_add_map_entry(unsigned int index) -{ - cpus_default_apic_id[index] = initial_lapicid(); -} - -/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ -int cpu_get_apic_id(int logical_cpu) -{ - if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) - return -1; - - return cpus_default_apic_id[logical_cpu]; -} - void cpu_initialize(void) { /* Because we busy wait at the printk spinlock. diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 8301e80..2909022 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -195,18 +195,16 @@ set_cpu_info(index, dev); - struct cpu_info *info = cpu_info(); - cpu_add_map_entry(info->index); - /* Fix up APIC id with reality. */ - info->cpu->path.apic.apic_id = lapicid(); + dev->path.apic.apic_id = lapicid(); + dev->path.apic.initial_lapicid = initial_lapicid(); if (cpu_is_intel()) - printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index, - info->cpu->path.apic.apic_id, get_current_microcode_rev()); + printk(BIOS_INFO, "AP: slot %u apic_id %x, MCU rev: 0x%08x\n", index, + dev->path.apic.apic_id, get_current_microcode_rev()); else - printk(BIOS_INFO, "AP: slot %zu apic_id %x\n", info->index, - info->cpu->path.apic.apic_id); + printk(BIOS_INFO, "AP: slot %u apic_id %x\n", index, + dev->path.apic.apic_id); /* Walk the flight plan */ ap_do_flight_plan(); @@ -547,6 +545,7 @@ printk(BIOS_CRIT, "Failed to find or allocate BSP struct device\n"); return CB_ERR; } + bsp->path.apic.initial_lapicid = initial_lapicid(); /* Find the device structure for the boot CPU. */ set_cpu_info(0, bsp); @@ -558,9 +557,6 @@ printk(BIOS_CRIT, "BSP index(%zd) != 0!\n", info->index); return CB_ERR; } - - /* Track BSP in cpu_map structures. */ - cpu_add_map_entry(info->index); return CB_SUCCESS; } @@ -748,11 +744,12 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) { - int i; struct smm_stub_params *stub_params = smm_params->stub_params; - for (i = 0; i < CONFIG_MAX_CPUS; i++) - stub_params->apic_id_to_cpu[i] = cpu_get_apic_id(i); + int i = 0; + for (struct device *dev = g_cpu_bus->children; dev; dev = dev->sibling) + if (dev->enabled) + stub_params->apic_id_to_cpu[i++] = dev->path.apic.initial_lapicid; } static enum cb_err install_relocation_handler(int num_cpus, size_t save_state_size) diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index f406e23..9185cc6 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -13,6 +13,7 @@ /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; + cpu_path.apic.initial_lapicid = apic_id; /* Update CPU in devicetree. */ if (enabled) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index a77cb33..fc662ee 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -7,11 +7,7 @@ #include <stdint.h> void cpu_initialize(void); -/* Returns default APIC id based on logical_cpu number or < 0 on failure. */ -int cpu_get_apic_id(int logical_cpu); uintptr_t cpu_get_lapic_addr(void); -/* Function to keep track of cpu default apic_id */ -void cpu_add_map_entry(unsigned int index); struct bus; int cpu_phys_address_size(void); diff --git a/src/include/device/path.h b/src/include/device/path.h index a1ea42c..c0df66b 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -73,6 +73,7 @@ }; struct apic_path { + unsigned int initial_lapicid; unsigned int apic_id; unsigned int package_id; unsigned int node_id; -- To view, visit https://review.coreboot.org/c/coreboot/+/64342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Gerrit-Change-Number: 64342 Gerrit-PatchSet: 29 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/mtl/romstage: Insert EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik, Wonkyu Kim, Paul Menzel, Kapil Porwal. Jay Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73191 ) Change subject: soc/intel/mtl/romstage: Insert EC boot timestamps ...................................................................... Patch Set 8: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73191/comment/9bed4ae5_6dccb473 PS6, Line 2: jaypatel256 > Please use your name. Done https://review.coreboot.org/c/coreboot/+/73191/comment/ed9ae612_4254b3d4 PS6, Line 10: Meteorlake > Meteor Lake Done https://review.coreboot.org/c/coreboot/+/73191/comment/9a9f2036_e6b64a93 PS6, Line 16: jaypatel256 > Ditto. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 Gerrit-Change-Number: 73191 Gerrit-PatchSet: 8 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:14:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs/config.lenovo_t400_vboot_and_debug: Move PT lower
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74219 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: configs/config.lenovo_t400_vboot_and_debug: Move PT lower ...................................................................... configs/config.lenovo_t400_vboot_and_debug: Move PT lower Bootblock gets too big, so move the RO page table downwards. Change-Id: I3f72d1639478eaaac09d7cfb3408944ac76307c4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74219 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M configs/config.lenovo_t400_vboot_and_debug 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400_vboot_and_debug index 39c17e6..f79d773 100644 --- a/configs/config.lenovo_t400_vboot_and_debug +++ b/configs/config.lenovo_t400_vboot_and_debug @@ -13,3 +13,4 @@ CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y CONFIG_VBOOT=y CONFIG_USE_EXP_X86_64_SUPPORT=y +CONFIG_ARCH_X86_64_PGTBL_LOC=0xfffe8000 -- To view, visit https://review.coreboot.org/c/coreboot/+/74219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f72d1639478eaaac09d7cfb3408944ac76307c4 Gerrit-Change-Number: 74219 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/lint/stable-017: Update full config pattern matching
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74220 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/lint/stable-017: Update full config pattern matching ...................................................................... util/lint/stable-017: Update full config pattern matching CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so use a different string: 'CONFIG_MAINBOARD_DIR'. Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M util/lint/lint-stable-017-configs 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/util/lint/lint-stable-017-configs b/util/lint/lint-stable-017-configs index 3f92f53..5be74457 100755 --- a/util/lint/lint-stable-017-configs +++ b/util/lint/lint-stable-017-configs @@ -12,7 +12,7 @@ # shellcheck source=helper_functions.sh . "${LINTDIR}/helper_functions.sh" -SYMBOLS='CONFIG_ARCH_\|CONFIG_MAINBOARD_HAS_' +SYMBOLS='CONFIG_MAINBOARD_DIR\|CONFIG_MAINBOARD_HAS_' #look for a couple of things that should only be set by select keywords for file in \ -- To view, visit https://review.coreboot.org/c/coreboot/+/74220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Gerrit-Change-Number: 74220 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/e02a41d3_8a98503a PS3, Line 8: > > I would directly write the whole thing (makes it easier to understand for me personally): […] ``` I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. ``` Than refer to it. ``` I'm intended to enable a bit which is described in the EDS. I don't think for enabling the bit related to 3-strike, I need to write whole paragraph about what is 3-strike error. ``` Than write down the source of your information. ``` If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ? ``` Thats a poor comparison. PCI is a very broad and very well known subject in Firmware/Coreboot community. It is referenced in numerous coreboot patches and can therefore be seen as "common knowledge". 3-three CATEER is a very specific thing that I assume is not known to "everyone" (at the very least its not known to me). ``` I have wrote the commit msg to explain what this patch does ``` Specifically I was missing the key information why disabling 3-three CATEER helps to do CPU traces. You say it does but you are not explaining why. At least one sentence about that would be enough for me. So I basically have to trust, that what you say is true or google for half an hour to check -> review time is much longer Maybe my suggestion was a bit overkill, but I don't see the harm in adding it. Better to have more information than less. -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:11:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Tarun Tuli, Jamie Ryu, Wonkyu Kim, Paul Menzel, Kapil Porwal. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73192 to look at the new patch set (#8). Change subject: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex ...................................................................... mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex Enables feature to record pre-reset boot time using EC boot timestamps. BUG=b:271012752 TEST=Pre-reset boot timestamps added to the timestamp table, verified using cbmem -t Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 --- M src/mainboard/google/rex/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73192/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/73192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 Gerrit-Change-Number: 73192 Gerrit-PatchSet: 8 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/mtl/romstage: Insert EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik, Wonkyu Kim, Kapil Porwal, Jay Patel. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73191 to look at the new patch set (#8). Change subject: soc/intel/mtl/romstage: Insert EC boot timestamps ...................................................................... soc/intel/mtl/romstage: Insert EC boot timestamps Calls the function to insert EC boot timestamps to the coreboot timestamp table for Meteor Lake SOC based on Kconfig flag SOC_INTEL_EC_BOOT_TIMESTAMPS. BUG=b:271012752 TEST=None Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/73191/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/73191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 Gerrit-Change-Number: 73191 Gerrit-PatchSet: 8 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: security/vboot: Don't add RO pagetables to RW_A/B
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74218 ) Change subject: security/vboot: Don't add RO pagetables to RW_A/B ...................................................................... security/vboot: Don't add RO pagetables to RW_A/B Currently this is only used in bootblock and expects a fixed offset. Change-Id: I3c4db6fffe3343f12383fe9585620ffefb01cf81 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74218 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/security/vboot/Makefile.inc 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 9e42ab1..ba83c3b 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -199,6 +199,7 @@ intel_fit \ intel_fit_ts \ fspt.bin \ + pagetables \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,\ $(if $(filter \ -- To view, visit https://review.coreboot.org/c/coreboot/+/74218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c4db6fffe3343f12383fe9585620ffefb01cf81 Gerrit-Change-Number: 74218 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: Documentation/mainboard/hp: Add more about internal flashing
by Václav Straka (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Václav Straka. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74248 to look at the new patch set (#5). Change subject: Documentation/mainboard/hp: Add more about internal flashing ...................................................................... Documentation/mainboard/hp: Add more about internal flashing Add a more detailed explanation of internal flashing on the HP Compaq 8200 Elite SFF. Signed-off-by: Vesek <venda.straka(a)gmail.com> Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 --- M Documentation/mainboard/hp/compaq_8200_sff.md A Documentation/mainboard/hp/compaq_8200_sff_jumper.jpg 2 files changed, 86 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74248/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636 Gerrit-Change-Number: 74248 Gerrit-PatchSet: 5 Gerrit-Owner: Václav Straka Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Václav Straka Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPU power sequencing to add Had...
by Eric Lai (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73896 ) Change subject: mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support ...................................................................... Patch Set 22: (1 comment) File src/mainboard/google/brya/variants/hades/variant.c: https://review.coreboot.org/c/coreboot/+/73896/comment/1d09922d_833919c7 PS22, Line 148: void variant_fill_ssdt(const struct device *dev) Since we have power.asl, why just put the _INI into it? It'd better all C code or all ASL code. -- To view, visit https://review.coreboot.org/c/coreboot/+/73896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Gerrit-Change-Number: 73896 Gerrit-PatchSet: 22 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:09:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023