coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/cmn/blk: Request pre-reset EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Wonkyu Kim, Subrata Banik, Dinesh Gehlot. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72931 to look at the new patch set (#14). Change subject: soc/intel/cmn/blk: Request pre-reset EC boot timestamps ...................................................................... soc/intel/cmn/blk: Request pre-reset EC boot timestamps coreboot requests pre-reset power signal timestamps to the EC. These timestamps are used to calculate pre-reset boot time and inserted into the coreboot timestamp table. The EC patches required to enable the feature in the EC: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612 In EC, it is also required to enable the feature in program config file by using SYSTEM_BOOT_TIME_LOGGING flag. BUG=b:271012752 TEST=Pre-reset timestamps added to cbmem timestamp table if flag enabled in Kconfig file and feature enabled from romstage for specific board. Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Iecb88eaa085759ea9430708d45abf1ca69727ce9 --- A src/soc/intel/common/block/ec_telemetry/Kconfig A src/soc/intel/common/block/ec_telemetry/Makefile.inc A src/soc/intel/common/block/ec_telemetry/ec_telemetry.c A src/soc/intel/common/block/include/intelblocks/ec_telemetry.h 4 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/72931/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/72931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb88eaa085759ea9430708d45abf1ca69727ce9 Gerrit-Change-Number: 72931 Gerrit-PatchSet: 14 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Enable AP <-> GSC communication
by Mark Hasemeyer (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74111 ) Change subject: mb/google/myst: Enable AP <-> GSC communication ...................................................................... Patch Set 26: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117 Gerrit-Change-Number: 74111 Gerrit-PatchSet: 26 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:50:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Ivy Jian, Maximilian Brune, Angel Pons, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/da10b544_91723d12 PS3, Line 8: > ``` > I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. > ``` > Than refer to it. Please try to understand we (googlers) working with Intel and have access to many docs (those are under NDA), we can't copy/paste some information from those docs and put them into the code review. Hence, we have to rely on the open source documentation and references. I can find some good reading here https://www.asset-intertech.com/resources/blog/2018/09/debug-of-intel-cater… in public Also, Intel doc:576242 to have more information. > ``` > I'm intended to enable a bit which is described in the EDS. I don't think for enabling the bit related to 3-strike, I need to write whole paragraph about what is 3-strike error. > ``` > Than write down the source of your information. Sure, i have added the doc number in the commit msg. > ``` > If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ? > ``` > Thats a poor comparison. PCI is a very broad and very well known subject in Firmware/Coreboot community. It is referenced in numerous coreboot patches and can therefore be seen as "common knowledge". > 3-three CATEER is a very specific thing that I assume is not known to "everyone" (at the very least its not known to me). I know this is a poor comparison but the point is hopefully clear, the purpose of the commit msg is not to educate about the technology. If the intention is to learn more on a certain topic, then a comment is more appropriate to know the source behind the technology like from where to learn more (isn't it ?). I can help here to share the possible information that I know. But as I said, some information are confidential and we can't just put those details to explain how CPU will collect more traces when 3-stike counter is disable vs enable. > > ``` > I have wrote the commit msg to explain what this patch does > ``` > Specifically I was missing the key information why disabling 3-three CATEER helps to do CPU traces. You say it does but you are not explaining why. At least one sentence about that would be enough for me. > So I basically have to trust, that what you say is true or google for half an hour to check -> review time is much longer I really don't know how to help here, those are very intel processor centric information and i won't be able to justify the expectation that you have here. > > Maybe my suggestion was a bit overkill, but I don't see the harm in adding it. Better to have more information than less. -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:49:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable eSPI SCI events
by Tim Van Patten (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74101 ) Change subject: mb/google/myst: Enable eSPI SCI events ...................................................................... Patch Set 19: (1 comment) File src/mainboard/google/myst/mainboard.c: https://review.coreboot.org/c/coreboot/+/74101/comment/60586bcd_c7dc06b5 PS19, Line 44: pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); > this is left over from guybrush LoL. Does that mean the line itself is unnecessary? Or is this just a comment on how hold the TODO is? -- To view, visit https://review.coreboot.org/c/coreboot/+/74101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Gerrit-Change-Number: 74101 Gerrit-PatchSet: 19 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:46:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn/blk: Request pre-reset EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Wonkyu Kim, Subrata Banik, Dinesh Gehlot. Jay Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72931 ) Change subject: soc/intel/cmn/blk: Request pre-reset EC boot timestamps ...................................................................... Patch Set 13: (1 comment) Patchset: PS8: > We should have bug for this. Jay, can you update bug info in commit message? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb88eaa085759ea9430708d45abf1ca69727ce9 Gerrit-Change-Number: 72931 Gerrit-PatchSet: 13 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:43:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Tarun Tuli, Jamie Ryu, Wonkyu Kim, Paul Menzel, Kapil Porwal. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73192 to look at the new patch set (#9). Change subject: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex ...................................................................... mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex Enables feature to record pre-reset boot time using EC boot timestamps. Additional patch required in EC to enable the feature: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4263103 In EC, it is also required to enable the feature in program config file using SYSTEM_BOOT_TIME_LOGGING flag. BUG=b:271012752 TEST=Pre-reset boot timestamps added to the timestamp table, verified using cbmem -t Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 --- M src/mainboard/google/rex/Kconfig 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73192/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/73192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b773fb4c7abfcb3c3ab061d970327987536fb2 Gerrit-Change-Number: 73192 Gerrit-PatchSet: 9 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/mtl/romstage: Insert EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik, Wonkyu Kim, Paul Menzel, Kapil Porwal. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Tarun Tuli, Jamie Ryu, Subrata Banik, Wonkyu Kim, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73191 to look at the new patch set (#9). Change subject: soc/intel/mtl/romstage: Insert EC boot timestamps ...................................................................... soc/intel/mtl/romstage: Insert EC boot timestamps Calls the function to insert EC boot timestamps to the coreboot timestamp table for Meteor Lake SOC based on Kconfig flag SOC_INTEL_EC_BOOT_TIMESTAMPS. BUG=b:271012752 TEST=None Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 --- M src/soc/intel/meteorlake/romstage/romstage.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/73191/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/73191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebda928a31d55a081f68b9833b66f757a9cd9aa7 Gerrit-Change-Number: 73191 Gerrit-PatchSet: 9 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cmn/blk: Request pre-reset EC boot timestamps
by Jay Patel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Subrata Banik, Dinesh Gehlot, Jay Patel. Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72931 to look at the new patch set (#13). Change subject: soc/intel/cmn/blk: Request pre-reset EC boot timestamps ...................................................................... soc/intel/cmn/blk: Request pre-reset EC boot timestamps coreboot requests pre-reset power signal timestamps to the EC. These timestamps are used to calculate pre-reset boot time and inserted into the coreboot timestamp table. The EC patches required to enable the feature in the EC: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612 In EC, it is also required to enable the feature in program config file by using SYSTEM_BOOT_TIME_LOGGING flag. BUG=b:271012752 TEST=Pre-reset timestamps added to cbmem timestamp table if flag enabled in Kconfig file and feature enabled from romstage for specific board. Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Iecb88eaa085759ea9430708d45abf1ca69727ce9 --- A src/soc/intel/common/block/ec_telemetry/Kconfig A src/soc/intel/common/block/ec_telemetry/Makefile.inc A src/soc/intel/common/block/ec_telemetry/ec_telemetry.c A src/soc/intel/common/block/include/intelblocks/ec_telemetry.h 4 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/72931/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/72931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb88eaa085759ea9430708d45abf1ca69727ce9 Gerrit-Change-Number: 72931 Gerrit-PatchSet: 13 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Angel Pons, Eric Lai, Lean Sheng Tan, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74158 to look at the new patch set (#5). Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... soc/intel/cmn/cpu: Add function to disable 3-strike CATERR In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74158/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: acpi/acpi.c: Follow spec more closely for MADT
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Benjamin Doron, Paul Menzel, Arthur Heymans. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69225 ) Change subject: acpi/acpi.c: Follow spec more closely for MADT ...................................................................... Patch Set 25: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f Gerrit-Change-Number: 69225 Gerrit-PatchSet: 25 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 06 Apr 2023 15:41:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023