coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Karol Zmyslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 17: (3 comments) File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/78b06e01_41c1957e PS12, Line 539: // Deep Sleep Well group > What was done? I see no change here. […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/66814f09_7577b4c2 PS12, Line 553: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", > ... […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/5a95828c_1f476cf4 PS12, Line 584: > I'm not against adding comments. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 17 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:18:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Dinesh Gehlot (Code Review) 06 Apr '23

06 Apr '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... soc/intel/cmd/block/cse: Add config option for storing fw version info This patch adds a configuration option, `CONFIG_CSE_FIRMWARE_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` option. BUG=b:273661726 Test=None Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74255/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index f1f53d6..8a2b37a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,6 +45,14 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_FIRMWARE_VERSION_STORAGE + bool + depends on DRIVERS_INTEL_ISH + help + This configuration option enables the storage of firmware version information in + CBMEM memory.This information can be used to identify the currently running firmware + partition version. + config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" depends on SOC_INTEL_COMMON_BLOCK_CSE -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Paul Menzel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Anand Vaikar, Fred Reitberger, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74075 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: Anand, thank you very much. -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 5 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:11:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/corsola: Add tablet Starmie as variant
by Paul Menzel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Ruihai Zhou, cong yang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74048 ) Change subject: mb/google/corsola: Add tablet Starmie as variant ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Gerrit-Change-Number: 74048 Gerrit-PatchSet: 7 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:10:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPU power sequencing to add Had...
by Tarun Tuli (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Subrata Banik, Kapil Porwal, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73896 ) Change subject: mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support ...................................................................... Patch Set 22: (1 comment) File src/mainboard/google/brya/variants/hades/variant.c: https://review.coreboot.org/c/coreboot/+/73896/comment/4100aa9d_95051fd2 PS22, Line 148: void variant_fill_ssdt(const struct device *dev) > Since we have power.asl, why just put the _INI into it? It'd better all C code or all ASL code. This is for logic meant to allow Agah devices to dynamically change these values at runtime based on board ID. It isn't really needed for Hades so why these seems a bit pointless here. Once we drop Agah, we can get rid of this completely. I'm trying to keep power.asl as compatible/common with both devices (for now) and this was the most straightforward. -- To view, visit https://review.coreboot.org/c/coreboot/+/73896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Gerrit-Change-Number: 73896 Gerrit-PatchSet: 22 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:02:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: Reland drivers/intel/dptf: Add multiple fan support under dptf
by Paul Menzel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Lance Zhao, Subrata Banik, Caveh Jalali, Reka Norman, Tim Wawrzynczak, Sumeet R Pawnikar, Maximilian Brune, Boris Mittelberg. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73249 ) Change subject: Reland drivers/intel/dptf: Add multiple fan support under dptf ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/include/acpi/acpigen_dptf.h: https://review.coreboot.org/c/coreboot/+/73249/comment/2f785198_baa52570 PS3, Line 128: speed > We have already added comment above for unit so would request to keep it as speed only here to make […] I prefer to avoid comments, and have it in a variable name. The variable names would still be short. But it’s personal preference, so of course it’s fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/73249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Gerrit-Change-Number: 73249 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 16:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Maximilian Brune (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Angel Pons, Ronak Kanabar. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/1c820686_92c2bb3c PS3, Line 8: > > ``` > > I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. > > ``` > > Than refer to it. > > Please try to understand we (googlers) working with Intel and have access to many docs (those are under NDA), we can't copy/paste some information from those docs and put them into the code review. Hence, we have to rely on the open source documentation and references. I can find some good reading here https://www.asset-intertech.com/resources/blog/2018/09/debug-of-intel-cater… in public > > Also, Intel doc:576242 to have more information. If you got the information from a NDA document, than of course you can just add intel document ID and be done with it. I would never suggest to break any kind of NDA. For me it just looked like this is general public knowledge (since it is also explained in the blog post you mentioned). > > ``` > > If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ? > > ``` > > Thats a poor comparison. PCI is a very broad and very well known subject in Firmware/Coreboot community. It is referenced in numerous coreboot patches and can therefore be seen as "common knowledge". > > 3-three CATEER is a very specific thing that I assume is not known to "everyone" (at the very least its not known to me). > > I know this is a poor comparison but the point is hopefully clear, the purpose of the commit msg is not to educate about the technology. If the intention is to learn more on a certain topic, then a comment is more appropriate to know the source behind the technology like from where to learn more (isn't it ?). I can help here to share the possible information that I know. But as I said, some information are confidential and we can't just put those details to explain how CPU will collect more traces when 3-stike counter is disable vs enable. I agree. A comment is much more useful for that. > > > > ``` > > I have wrote the commit msg to explain what this patch does > > ``` > > Specifically I was missing the key information why disabling 3-three CATEER helps to do CPU traces. You say it does but you are not explaining why. At least one sentence about that would be enough for me. > > So I basically have to trust, that what you say is true or google for half an hour to check -> review time is much longer > > I really don't know how to help here, those are very intel processor centric information and i won't be able to justify the expectation that you have here. I think you misunderstood me. I don't expect you to write how CPU tracing works. Before reading this I was under the assumption that JTAG assisted hardware tracing is basically almost always possible, not matter what state the system is in. Therefore it was hard for me to grasp why a CATERR is preventing me from doing a proper CPU trace. Apparently according to the blog post, the JTAG debugger cannot put the hardware into probe mode then, but that wasn't obvious to me and therefore my confusion. But I don't want to prolong your CL any longer and its only a minor problem for me anyway (despite how far the discussion went now). -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 16:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable variants for Myst
by Karthik Ramasubramanian (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74098 ) Change subject: mb/google/myst: Enable variants for Myst ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Gerrit-Change-Number: 74098 Gerrit-PatchSet: 15 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 16:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Build for chromeOS
by Karthik Ramasubramanian (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74097 ) Change subject: mb/google/myst: Build for chromeOS ...................................................................... Patch Set 15: Code-Review+2 (1 comment) File src/mainboard/google/myst/chromeos.c: https://review.coreboot.org/c/coreboot/+/74097/comment/2bde321c_48852462 PS15, Line 9: void fill_lb_gpios(struct lb_gpios *gpios) {} Not sure you even need this if this is going to be empty since VBOOT_NO_BOARD_SUPPORT will apply the same - https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he… Is there somewhere up the CL stack you remove VBOOT_NO_BOARD_SUPPORT config? -- To view, visit https://review.coreboot.org/c/coreboot/+/74097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Gerrit-Change-Number: 74097 Gerrit-PatchSet: 15 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 16:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023