coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program ...................................................................... soc/intel/meteorlake: Enable VMX using coreboot CPU feature program This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization if not done by FSP (based on DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake SoC based platform. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/cpu.c 2 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 9d9a600..d4abed8 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -350,6 +350,8 @@ /* Energy-Performance Preference (HWP feature) */ bool enable_energy_perf_pref; uint8_t energy_perf_pref_value; + + bool disable_vmx; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index fa1b83f..bc7f7c7 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -145,6 +145,9 @@ disable_three_strike_error(); set_aesni_lock(); + + /* Enable VMX */ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/poppy/var/nami: Fix stylus runtime detection
by Sean Rhodes (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Matt DeVillier, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74234 ) Change subject: mb/google/poppy/var/nami: Fix stylus runtime detection ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Gerrit-Change-Number: 74234 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 19:34:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set AES-NI Lock
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74160 ) Change subject: soc/intel/meteorlake: Set AES-NI Lock ...................................................................... soc/intel/meteorlake: Set AES-NI Lock This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 6d64e5b..fa1b83f 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -143,6 +143,8 @@ if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) { /* Disable 3-strike error */ disable_three_strike_error(); + + set_aesni_lock(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Gerrit-Change-Number: 74160 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Disable 3-strike error
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74159 ) Change subject: soc/intel/meteorlake: Disable 3-strike error ...................................................................... soc/intel/meteorlake: Disable 3-strike error This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/cpu.c 1 file changed, 31 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index 691f50d..6d64e5b 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -139,6 +139,11 @@ if (CONFIG(INTEL_TME) && is_tme_supported()) set_tme_core_activate(); + + if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) { + /* Disable 3-strike error */ + disable_three_strike_error(); + } } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/74159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Gerrit-Change-Number: 74159 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Allow to drop redundant CPU feature programming
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74167 ) Change subject: soc/intel/meteorlake: Allow to drop redundant CPU feature programming ...................................................................... soc/intel/meteorlake: Allow to drop redundant CPU feature programming This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of this feature programming is getting performed today in scope of coreboot doing MP Init. Running this redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) results in CPU exception (for example: attempting to reprogram CPU feature lock MSR is causing CPU exception). SoC users should select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is by default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. At present, this option does not do anything unless any platform eventually decides to drop FSP feature programming module and choose coreboot CPU feature programming over it. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index b29b3bc..3d99f81 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -364,4 +364,25 @@ help Set this option if debug build of FSP is used. +config DROP_CPU_FEATURE_PROGRAM_IN_FSP + bool + default y if MP_SERVICES_PPI_V2_NOOP + default n + help + This is to avoid FSP running basic CPU feature programming on BSP + and on APs using the "CpuFeaturesPei.efi" module. The feature programming + includes enabling x2APIC, MCA, MCE and Turbo etc. + + Most of these feature programming are getting performed today in scope + of coreboot doing MP Init. Running these redundant programming in scope + of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) would + results in CPU exception. + + SoC users to select this config after dropping "CpuFeaturesPei.ffs" module + from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional + feature programming on BSP and APs. + + This feature is default enabled, in case of "coreboot running MP init" + aka MP_SERVICES_PPI_V2_NOOP config is selected. + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Gerrit-Change-Number: 74167 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Lean Sheng Tan (Code Review) 06 Apr '23

06 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... soc/intel/cmn/cpu: Add function to disable 3-strike CATERR In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index bfa4818..3f0ee67 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -569,3 +569,12 @@ { return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ; } + +void disable_three_strike_error(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo = msr.lo | DISABLE_CPU_ERROR; + wrmsr(MSR_PREFETCH_CTL, msr); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index c72e1ea..38c43d8 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -222,4 +222,11 @@ * Returns true if Key Locker feature is supported otherwise false. */ bool is_keylocker_supported(void); + +/* + * This function prevents the Three Strike Counter from incrementing. + * It helps to collect more useful CPU traces for debugging. + */ +void disable_three_strike_error(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index d4d8732..9f95e9f 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -35,6 +35,7 @@ #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2) +#define DISABLE_CPU_ERROR (1 << 11) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MISC_PWR_MGMT_ISST_EN (1 << 6) -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: Lower log level for TDP value to DEBUG
by Paul Menzel (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74271 ) Change subject: soc/amd/mendocino: Lower log level for TDP value to DEBUG ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/mendocino/fsp_misc_data_hob.c: https://review.coreboot.org/c/coreboot/+/74271/comment/3f92c712_4436b9e1 PS1, Line 51: printk(BIOS_DEBUG, "fsp_misc_data->smu_power_and_thm_limit = 0x%08X\n", > I'm not entirely familiar with the specifics of the logging output. […] See the definitions in `src/commonlib/include/commonlib/loglevel.h`. By default, the log level is debug. -- To view, visit https://review.coreboot.org/c/coreboot/+/74271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f6293fd47633dfdbdae37b7257f47a5a4bb29c Gerrit-Change-Number: 74271 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Apr 2023 19:27:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1
by Elyes Haouas (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Paul Menzel, Angel Pons, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Jason Glenesk, Martin L Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73792 to look at the new patch set (#10). Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1 ...................................................................... crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1 Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/clang-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/cmake-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/llvm-16.0.1.src.tar.xz.cksum 11 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73792/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/73792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Gerrit-Change-Number: 73792 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'
by Elyes Haouas (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Felix Singer, Stefan Ott, Alexander Couzens. Hello Felix Singer, Stefan Ott, build bot (Jenkins), Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73810 to look at the new patch set (#6). Change subject: ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int' ...................................................................... ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/ec/lenovo/pmh7/chip.h M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M util/autoport/ec_lenovo.go 21 files changed, 60 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/73810/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/73810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Gerrit-Change-Number: 73810 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'
by Elyes Haouas (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev. Hello Felix Singer, build bot (Jenkins), Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73796 to look at the new patch set (#7). Change subject: sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' ...................................................................... sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h 11 files changed, 36 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/73796/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/73796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Gerrit-Change-Number: 73796 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2023