coreboot-gerrit April 2023

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[S] Change in coreboot[master]: util/cbfstool: Correct the definition of struct e820entry
by Bill XIE (Code Review) 06 Apr '23

06 Apr '23

Bill XIE has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74270 ) Change subject: util/cbfstool: Correct the definition of struct e820entry ...................................................................... util/cbfstool: Correct the definition of struct e820entry In order to accord with grub (see include/grub/i386/linux.h) and comments for offsets of members of struct linux_params, struct e820entry should be defined as __packed, otherwise, sizeof(struct linux_params) will become 4224 (0x1080). Fortunately, the affected area is usually not occupied. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I09955c90e4eec337adca383e628a8821075381d6 --- M util/cbfstool/linux.h 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74270/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Gerrit-Change-Number: 74270 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/cbfstool: Correct the definition of struct e820entry
by Bill XIE (Code Review) 06 Apr '23

06 Apr '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74270 ) Change subject: util/cbfstool: Correct the definition of struct e820entry ...................................................................... util/cbfstool: Correct the definition of struct e820entry In order to accord with grub (see include/grub/i386/linux.h) and comments for offsets of members of struct linux_params, struct e820entry should be defined as __packed. Fortunately, the affected area is usually not occupied. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I09955c90e4eec337adca383e628a8821075381d6 --- M util/cbfstool/linux.h 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74270/1 diff --git a/util/cbfstool/linux.h b/util/cbfstool/linux.h index dc4575c..2905f35 100644 --- a/util/cbfstool/linux.h +++ b/util/cbfstool/linux.h @@ -27,7 +27,7 @@ #define E820_RESERVED 2 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ #define E820_NVS 4 -}; +} __packed; /* The header of Linux/i386 kernel */ struct linux_header { -- To view, visit https://review.coreboot.org/c/coreboot/+/74270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Gerrit-Change-Number: 74270 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Dinesh Gehlot (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Subrata Banik, Kapil Porwal. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/74255/comment/d1b6217c_156849ed PS1, Line 48: SOC_INTEL_FIRMWARE_VERSION_STORAGE > SOC_INTEL_GET_FIRMWARE_VERSIONS_FROM_CSE Ack https://review.coreboot.org/c/coreboot/+/74255/comment/ad940e8a_ec1e2011 PS1, Line 52: This configuration option enables the storage of firmware version information in > we need to highlight that we are referring here the FW sits inside the CSE partitions Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 18:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Dinesh Gehlot (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Hello build bot (Jenkins), Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74255 to look at the new patch set (#2). Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... soc/intel/cmd/block/cse: Add config option for storing fw version info This patch adds a configuration option, `CONFIG_CSE_FIRMWARE_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` option. BUG=b:273661726 Test=None Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74255/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: amd/mendocino/root_complex: Restrict DPTC to 15W boards
by Felix Held (Code Review) 06 Apr '23

06 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74127 ) Change subject: amd/mendocino/root_complex: Restrict DPTC to 15W boards ...................................................................... amd/mendocino/root_complex: Restrict DPTC to 15W boards Restrict DPTC to 15W boards, since we only have 15W values defined in the devicetree. This will revert the 6W boards back to their default values, rather than (incorrectly) configuring them with 15W values. BUG=b:253301653 TEST=Verify DPTC values are set for 15W boards TEST=Verify DPTC values are set not set for 6W boards Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Signed-off-by: Tim Van Patten <timvp(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74127 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/root_complex.c 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6217246..53a245b 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -12,11 +12,13 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <fsp/amd_misc_data.h> #include <fsp/util.h> #include <soc/iomap.h> #include <stdint.h> #include "chip.h" +#define TDP_15W 15 #define DPTC_TOTAL_UPDATE_PARAMS 13 struct dptc_input { @@ -367,7 +369,18 @@ static void root_complex_fill_ssdt(const struct device *device) { + uint32_t tdp = 0; + acpi_fill_root_complex_tom(device); + + if (get_amd_smu_reported_tdp(&tdp) != CB_SUCCESS) { + /* Unknown TDP, so return rather than setting invalid values. */ + return; + } + /* TODO(b/249359574): Add support for 6W DPTC values. */ + if (tdp != TDP_15W) + return; + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) acipgen_dptci(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7 Gerrit-Change-Number: 74127 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit
by Felix Held (Code Review) 06 Apr '23

06 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74126 ) Change subject: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit ...................................................................... soc/amd/mendocino: Reinterpret smu_power_and_thm_limit The FSP will return the TDP in the format 0xX0000, where 'X' is the value we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret the value so the caller just sees the TDP directly, without needing to re-interpret things themselves. BUG=b:253301653 TEST=Manually verify value is correct Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Signed-off-by: Tim Van Patten <timvp(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74126 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/fsp_misc_data_hob.c 1 file changed, 29 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/mendocino/fsp_misc_data_hob.c b/src/soc/amd/mendocino/fsp_misc_data_hob.c index 103f821..3b51fd8 100644 --- a/src/soc/amd/mendocino/fsp_misc_data_hob.c +++ b/src/soc/amd/mendocino/fsp_misc_data_hob.c @@ -43,7 +43,14 @@ if (get_amd_misc_data_hob(&fsp_misc_data, AMD_MISC_DATA_VERSION) != CB_SUCCESS) return CB_ERR; - *tdp = fsp_misc_data->smu_power_and_thm_limit; + /* + * The FSP will return the TDP in the format 0xX0000, where 'X' is the value + * we're interested in. For example: 0xF0000 (15W), 0x60000 (6W). Re-interpret + * the value so the caller just sees the TDP. + */ + printk(BIOS_INFO, "fsp_misc_data->smu_power_and_thm_limit = 0x%08X\n", + fsp_misc_data->smu_power_and_thm_limit); + *tdp = fsp_misc_data->smu_power_and_thm_limit >> 16; return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d Gerrit-Change-Number: 74126 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Anil Kumar K (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Paul Menzel, Eric Lai, Uday Bhat, Anil Kumar K, Jairaj Arava. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 15: (1 comment) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/72881/comment/6e75a7aa_dfa03a8d PS15, Line 77: if (!fw_config_is_provisioned()) { > We can combine this into FW config probe. […] Hi Eric. this is a cleanup and shall we have it part of a seperate patch? Not related to BT enablement . -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 15 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:31:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmd/block/cse: Add config option for storing fw version info
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74255 ) Change subject: soc/intel/cmd/block/cse: Add config option for storing fw version info ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/74255/comment/7290bee0_741b5887 PS1, Line 48: SOC_INTEL_FIRMWARE_VERSION_STORAGE SOC_INTEL_GET_FIRMWARE_VERSIONS_FROM_CSE https://review.coreboot.org/c/coreboot/+/74255/comment/2379d102_6131b157 PS1, Line 52: This configuration option enables the storage of firmware version information in we need to highlight that we are referring here the FW sits inside the CSE partitions -- To view, visit https://review.coreboot.org/c/coreboot/+/74255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78fef45fd2940536b3e91cfd4d184b7635238499 Gerrit-Change-Number: 74255 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:28:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Ivy Jian, Maximilian Brune, Angel Pons, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/ff7f20a1_b1344050 PS3, Line 8: > > > ``` > > > I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that. > > > ``` > > > Than refer to it. > > > > Please try to understand we (googlers) working with Intel and have access to many docs (those are under NDA), we can't copy/paste some information from those docs and put them into the code review. Hence, we have to rely on the open source documentation and references. I can find some good reading here https://www.asset-intertech.com/resources/blog/2018/09/debug-of-intel-cater… in public > > > > Also, Intel doc:576242 to have more information. > > If you got the information from a NDA document, than of course you can just add intel document ID and be done with it. I would never suggest to break any kind of NDA. For me it just looked like this is general public knowledge (since it is also explained in the blog post you mentioned). > > > > ``` > > > If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ? > > > ``` > > > Thats a poor comparison. PCI is a very broad and very well known subject in Firmware/Coreboot community. It is referenced in numerous coreboot patches and can therefore be seen as "common knowledge". > > > 3-three CATEER is a very specific thing that I assume is not known to "everyone" (at the very least its not known to me). > > > > I know this is a poor comparison but the point is hopefully clear, the purpose of the commit msg is not to educate about the technology. If the intention is to learn more on a certain topic, then a comment is more appropriate to know the source behind the technology like from where to learn more (isn't it ?). I can help here to share the possible information that I know. But as I said, some information are confidential and we can't just put those details to explain how CPU will collect more traces when 3-stike counter is disable vs enable. > > I agree. A comment is much more useful for that. > > > > > > > ``` > > > I have wrote the commit msg to explain what this patch does > > > ``` > > > Specifically I was missing the key information why disabling 3-three CATEER helps to do CPU traces. You say it does but you are not explaining why. At least one sentence about that would be enough for me. > > > So I basically have to trust, that what you say is true or google for half an hour to check -> review time is much longer > > > > I really don't know how to help here, those are very intel processor centric information and i won't be able to justify the expectation that you have here. > > I think you misunderstood me. I don't expect you to write how CPU tracing works. Before reading this I was under the assumption that JTAG assisted hardware tracing is basically almost always possible, not matter what state the system is in. Therefore it was hard for me to grasp why a CATERR is preventing me from doing a proper CPU trace. Apparently according to the blog post, the JTAG debugger cannot put the hardware into probe mode then, but that wasn't obvious to me and therefore my confusion. > > But I don't want to prolong your CL any longer and its only a minor problem for me anyway (despite how far the discussion went now). Thanks for the discussion. -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/variants/hades: Update GPU power sequencing to add Had...
by Subrata Banik (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73896 ) Change subject: mb/google/brya/variants/hades: Update GPU power sequencing to add Hades support ...................................................................... Patch Set 22: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Gerrit-Change-Number: 73896 Gerrit-PatchSet: 22 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 17:21:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023