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I'd like you to reexamine a change. Please visit
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Change subject: AMD binaryPI: Use madt_ioapic_from_hw()
......................................................................
AMD binaryPI: Use madt_ioapic_from_hw()
Read IOAPIC ID and number of interrupts from programmed registers.
Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/northbridge/amd/pi/00730F01/acpi_tables.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/00730F01/state_machine.c
D src/southbridge/amd/pi/hudson/ioapic.h
M src/southbridge/amd/pi/hudson/sm.c
5 files changed, 19 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55570/12
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
......................................................................
soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.
Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample whichcauses idle delay while waiting
for EOP response.
The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd.
This patch helps to create ample duration between CSE EOP command
being sent and response being captured.
TEST=Able to boot google/marasov EVT sku to ChromeOS and observed
~30ms of boot time savings (across warm and cold reset scenarios).
Without this patch:
963:returning from FspMultiPhaseSiInit 907,326 (97,293)
...
...
115:finished elog init 967,343 (2,581)
942:before sending EOP to ME 967,821 (478)
…
16:finished LZMA decompress (ignore for x86) 1,017,937 (12,135)
943:after sending EOP to ME 1,067,799 (49,861)
…
…
1101:jumping to kernel 1,144,587 (13,734)
Total Time: 1,144,549
With this patch:
963:returning from FspMultiPhaseSiInit 918,291 (97,320)
942:before sending EOP to ME 918,522 (230)
...
...
16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)
943:after sending EOP to ME 1,033,456 (3,980)
...
...
1101:jumping to kernel 1,111,410 (14,007)
Total Time: 1,111,375
Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/cse/cse.c
2 files changed, 68 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74293/2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69222 )
Change subject: cpu/x86/topology: Add code to fill in topology on struct path
......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23:
Felix: There was something about CPUID leaf 0xb with AMD. It is reported as implemented but still does not report the topology ?
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70270 )
Change subject: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
superseded with CB:73390
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74293 )
Change subject: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
......................................................................
Patch Set 1:
(5 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173739):
https://review.coreboot.org/c/coreboot/+/74293/comment/ffe6f458_84372139
PS1, Line 32: …
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173739):
https://review.coreboot.org/c/coreboot/+/74293/comment/ed895dab_1fcb9b73
PS1, Line 35: Total Time: 1,144,549
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173739):
https://review.coreboot.org/c/coreboot/+/74293/comment/05f93920_195bdf05
PS1, Line 41: 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173739):
https://review.coreboot.org/c/coreboot/+/74293/comment/62ec9856_32da7e4b
PS1, Line 44: ...
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173739):
https://review.coreboot.org/c/coreboot/+/74293/comment/f42e4288_ad80777a
PS1, Line 47: Total Time: 1,111,375
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74293 )
Change subject: soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
......................................................................
soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.
Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample whichcauses idle delay while waiting
for EOP response.
The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd.
This patch helps to create ample duration between CSE EOP command
being sent and response being captured.
TEST=Able to boot google/marasov EVT sku to ChromeOS and observed
~30ms of boot time savings (across warm and cold reset scenarios).
Without this patch:
942:before sending EOP to ME 967,821 (478)
…
16:finished LZMA decompress (ignore for x86) 1,017,937 (12,135)
943:after sending EOP to ME 1,067,799 (49,861)
…
…
1101:jumping to kernel 1,144,587 (13,734)
Total Time: 1,144,549
With this patch:
942:before sending EOP to ME 918,522 (230)
...
16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)
943:after sending EOP to ME 1,033,456 (3,980)
...
...
1101:jumping to kernel 1,111,410 (14,007)
Total Time: 1,111,375
Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/chip.c
M src/soc/intel/common/block/cse/cse.c
2 files changed, 63 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74293/1
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index e0aa983..25b412e 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -203,7 +203,8 @@
* current boot sequence) to reduce message response time from CSE hence moving
* sending EOP to earlier stage.
*/
- if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) {
+ if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
+ CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
printk(BIOS_INFO, "Sending EOP early from SoC\n");
cse_send_end_of_post();
}
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 6c4bb73..1aa3454 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1424,22 +1424,23 @@
*/
static void cse_final(struct device *dev)
{
- /* SoC user decided to send EOP late */
- if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+ /*
+ * SoC user can have two options for sending EOP:
+ * 1. Choose to send EOP late
+ * 2. Choose to send EOP cmd asynchronously
+ *
+ * In case of sending EOP in asynchronous mode, the EOP command
+ * has most likely not been completed yet. The finalization steps
+ * will be run once the EOP command has successfully been completed.
+ */
+ if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) ||
+ CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
return;
/* 1. Send EOP to CSE if not done.*/
if (CONFIG(SOC_INTEL_CSE_SET_EOP))
cse_send_end_of_post();
- /*
- * In asynchronous mode, the EOP command has most likely not been
- * completed yet. Finalization steps will be run once the EOP command
- * has successfully been completed.
- */
- if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC))
- return;
-
if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT))
cse_final_ready_to_boot();
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Change subject: soc/amd/spi: Mmap 32M/64M flash
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS5:
> I have a feeling that the current mmap API is only prepared for permanently […]
For the newest SOC and 32M or 64M SPI flash.
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/5284c59f_df5a0c3d
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
How was this value determined?
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Change subject: util/docker: Decouple coreboot-sdk from other projects
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: util/docker/jenkins-node: Drop Zephyr SDK
......................................................................
Patch Set 4:
This change is ready for review.
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