coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Tarun Tuli, Dtrain Hsu, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74246 ) Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Gerrit-Change-Number: 74246 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 02:21:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
by Derek Huang (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Tarun Tuli, Dtrain Hsu, Subrata Banik, Kapil Porwal. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74246 ) Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Gerrit-Change-Number: 74246 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 02:00:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74064 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR ...................................................................... soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=boot with following logs [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74064 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/spi.c 1 file changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/spi.c b/src/soc/mediatek/mt8188/spi.c index 56efec5..0596bb9 100644 --- a/src/soc/mediatek/mt8188/spi.c +++ b/src/soc/mediatek/mt8188/spi.c @@ -6,6 +6,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> @@ -105,6 +106,14 @@ for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select); gpio_set_mode(ptr[i].gpio, ptr[i].func); + + if (gpio_set_driving(ptr[i].gpio, GPIO_DRV_8_MA) < 0) + printk(BIOS_ERR, + "%s: failed to set pin drive to 8 mA for %d\n", + __func__, ptr[i].gpio.id); + else + printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__, + gpio_get_driving(ptr[i].gpio)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 11 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/mediatek/mt8186: Move GPIO driving-related functions to common
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74068 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8186: Move GPIO driving-related functions to common ...................................................................... soc/mediatek/mt8186: Move GPIO driving-related functions to common Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74068 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h M src/soc/mediatek/mt8188/include/soc/gpio.h 5 files changed, 143 insertions(+), 131 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index daed555..e8a50b2 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -173,3 +173,110 @@ write32(&mtk_eint->mask_clr.regs[pos], mask); } + +static inline bool is_valid_drv(uint8_t drv) +{ + return drv <= GPIO_DRV_16_MA; +} + +static inline bool is_valid_drv_adv(enum gpio_drv_adv drv) +{ + return drv <= GPIO_DRV_ADV_1_MA && drv >= GPIO_DRV_ADV_125_UA; +} + +int gpio_set_driving(gpio_t gpio, uint8_t drv) +{ + uint32_t mask; + const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); + void *reg, *reg_adv, *reg_addr; + + if (!info) + return -1; + + if (!is_valid_drv(drv)) + return -1; + + if (info->width == 0) + return -1; + + mask = BIT(info->width) - 1; + /* Check setting value is not beyond width */ + if ((uint32_t)drv > mask) + return -1; + + reg_addr = gpio_find_reg_addr(gpio); + reg = reg_addr + info->offset; + clrsetbits32(reg, mask << info->shift, drv << info->shift); + + /* Disable EH if supported */ + if (adv_info && adv_info->width != 0) { + reg_adv = reg_addr + adv_info->offset; + clrbits32(reg_adv, BIT(adv_info->shift)); + } + + return 0; +} + +int gpio_get_driving(gpio_t gpio) +{ + const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); + void *reg; + + if (!info) + return -1; + + if (info->width == 0) + return -1; + + reg = gpio_find_reg_addr(gpio) + info->offset; + return (read32(reg) >> info->shift) & (BIT(info->width) - 1); +} + +int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv) +{ + uint32_t mask; + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); + void *reg_adv; + + if (!adv_info) + return -1; + + if (!is_valid_drv_adv(drv)) + return -1; + + if (adv_info->width == 0) + return -1; + + /* Not include EH bit (the lowest bit) */ + if ((uint32_t)drv > (BIT(adv_info->width - 1) - 1)) + return -1; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + mask = BIT(adv_info->width) - 1; + /* EH enable */ + drv = (drv << 1) | BIT(0); + + clrsetbits32(reg_adv, mask << adv_info->shift, drv << adv_info->shift); + + return 0; +} + +int gpio_get_driving_adv(gpio_t gpio) +{ + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); + void *reg_adv; + uint32_t drv; + + if (!adv_info) + return -1; + + if (adv_info->width == 0) + return -1; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + drv = (read32(reg_adv) >> adv_info->shift) & (BIT(adv_info->width) - 1); + + /* Drop EH bit */ + return drv >> 1; +} diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 993dbe6..b12d9c9 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -33,6 +33,17 @@ GPIO_DRV_ADV_1_MA = 3, }; +enum gpio_drv { + GPIO_DRV_2_MA = 0, + GPIO_DRV_4_MA = 1, + GPIO_DRV_6_MA = 2, + GPIO_DRV_8_MA = 3, + GPIO_DRV_10_MA = 4, + GPIO_DRV_12_MA = 5, + GPIO_DRV_14_MA = 6, + GPIO_DRV_16_MA = 7, +}; + struct gpio_drv_info { uint8_t offset; uint8_t shift; @@ -44,6 +55,9 @@ void gpio_set_mode(gpio_t gpio, int mode); void *gpio_find_reg_addr(gpio_t gpio); +const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id); +const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id); + /* Normal driving function */ int gpio_set_driving(gpio_t gpio, uint8_t drv); int gpio_get_driving(gpio_t gpio); diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c index 0dad342..a92349c 100644 --- a/src/soc/mediatek/mt8186/gpio.c +++ b/src/soc/mediatek/mt8186/gpio.c @@ -278,7 +278,7 @@ return reg_addr; } -static const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) +const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) { if (ENV_BOOTBLOCK) { uint32_t id; @@ -321,7 +321,7 @@ } } -static const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) +const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) { if (ENV_BOOTBLOCK) { return NULL; @@ -331,111 +331,3 @@ return &gpio_driving_adv_info[raw_id]; } } - -static inline bool is_valid_drv(uint8_t drv) -{ - return drv <= GPIO_DRV_16_MA; -} - -static inline bool is_valid_drv_adv(enum gpio_drv_adv drv) -{ - return drv <= GPIO_DRV_ADV_1_MA && drv >= GPIO_DRV_ADV_125_UA; -} - -int gpio_set_driving(gpio_t gpio, uint8_t drv) -{ - uint32_t mask; - const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); - const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); - void *reg, *reg_adv, *reg_addr; - - if (!info) - return -1; - - if (!is_valid_drv(drv)) - return -1; - - if (info->width == 0) - return -1; - - mask = BIT(info->width) - 1; - /* Check setting value is not beyond width */ - if ((uint32_t)drv > mask) - return -1; - - reg_addr = gpio_find_reg_addr(gpio); - reg = reg_addr + info->offset; - clrsetbits32(reg, mask << info->shift, drv << info->shift); - - /* Disable EH if supported */ - if (adv_info && adv_info->width != 0) { - reg_adv = reg_addr + adv_info->offset; - clrbits32(reg_adv, BIT(adv_info->shift)); - } - - return 0; -} - -int gpio_get_driving(gpio_t gpio) -{ - const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); - void *reg; - - if (!info) - return -1; - - reg = gpio_find_reg_addr(gpio) + info->offset; - if (info->width == 0) - return -1; - - return (read32(reg) >> info->shift) & (BIT(info->width) - 1); -} - -int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv) -{ - uint32_t mask; - const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); - void *reg_adv; - - if (!adv_info) - return -1; - - if (!is_valid_drv_adv(drv)) - return -1; - - reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; - - if (adv_info->width == 0) - return -1; - - /* Not include EH bit (the lowest bit) */ - if ((uint32_t)drv > (BIT(adv_info->width - 1) - 1)) - return -1; - - mask = BIT(adv_info->width) - 1; - /* EH enable */ - drv = (drv << 1) | BIT(0); - - clrsetbits32(reg_adv, mask << adv_info->shift, drv << adv_info->shift); - - return 0; -} - -int gpio_get_driving_adv(gpio_t gpio) -{ - const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); - void *reg_adv; - uint32_t drv; - - if (!adv_info) - return -1; - - reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; - if (adv_info->width == 0) - return -1; - - drv = (read32(reg_adv) >> adv_info->shift) & (BIT(adv_info->width) - 1); - - /* Drop EH bit */ - return drv >> 1; -} diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index 1377e01..4ce1e98 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -20,17 +20,6 @@ GPIO_MODE_BITS = 4, }; -enum gpio_drv { - GPIO_DRV_2_MA = 0, - GPIO_DRV_4_MA = 1, - GPIO_DRV_6_MA = 2, - GPIO_DRV_8_MA = 3, - GPIO_DRV_10_MA = 4, - GPIO_DRV_12_MA = 5, - GPIO_DRV_14_MA = 6, - GPIO_DRV_16_MA = 7, -}; - #define GPIO_ID(name) PAD_##name##_ID #define PIN(id, name, flag, bit, base, offset, \ diff --git a/src/soc/mediatek/mt8188/include/soc/gpio.h b/src/soc/mediatek/mt8188/include/soc/gpio.h index 803fcf4..8767e0f 100644 --- a/src/soc/mediatek/mt8188/include/soc/gpio.h +++ b/src/soc/mediatek/mt8188/include/soc/gpio.h @@ -19,16 +19,6 @@ MAX_GPIO_MODE_PER_REG = 8, GPIO_MODE_BITS = 4, }; -enum gpio_drv { - GPIO_DRV_2_MA = 0, - GPIO_DRV_4_MA = 1, - GPIO_DRV_6_MA = 2, - GPIO_DRV_8_MA = 3, - GPIO_DRV_10_MA = 4, - GPIO_DRV_12_MA = 5, - GPIO_DRV_14_MA = 6, - GPIO_DRV_16_MA = 7, -}; #define PIN(id, name, flag, bit, base, offset, \ func1, func2, func3, func4, func5, func6, func7) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/74068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Gerrit-Change-Number: 74068 Gerrit-PatchSet: 7 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/mediatek/mt8188: Add GPIO driving functions
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74063 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: Add GPIO driving functions ...................................................................... soc/mediatek/mt8188: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74063 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/gpio.c 1 file changed, 270 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/gpio.c b/src/soc/mediatek/mt8188/gpio.c index ecadb3f..a98f7ef 100644 --- a/src/soc/mediatek/mt8188/gpio.c +++ b/src/soc/mediatek/mt8188/gpio.c @@ -8,6 +8,227 @@ #include <device/mmio.h> #include <gpio.h> +#define SPI_AP_GPIO_BASE 125 + +enum { + SPI_AP_CLK_ROM = 0, + SPI_AP_CS_ROM_L = 1, + SPI_AP_DO_ROM_DI = 2, + SPI_AP_DI_ROM_DO = 3, +}; + +static const struct gpio_drv_info bootblock_gpio_driving_info[] = { + [SPI_AP_CLK_ROM] = { 0x20, 24, 3, }, + [SPI_AP_CS_ROM_L] = { 0x20, 24, 3, }, + [SPI_AP_DO_ROM_DI] = { 0x20, 24, 3, }, + [SPI_AP_DI_ROM_DO] = { 0x20, 27, 3, }, +}; + +static const struct gpio_drv_info gpio_driving_info[] = { + [0] = { 0x00, 24, 3, }, + [1] = { 0x00, 27, 3, }, + [2] = { 0x10, 0, 3, }, + [3] = { 0x10, 3, 3, }, + [4] = { 0x20, 9, 3, }, + [5] = { 0x20, 9, 3, }, + [6] = { 0x20, 9, 3, }, + [7] = { 0x10, 6, 3, }, + [8] = { 0x10, 9, 3, }, + [9] = { 0x10, 12, 3, }, + [10] = { 0x10, 15, 3, }, + [11] = { 0x20, 12, 3, }, + [12] = { 0x10, 24, 3, }, + [13] = { 0x10, 27, 3, }, + [14] = { 0x20, 0, 3, }, + [15] = { 0x20, 3, 3, }, + [16] = { 0x10, 15, 3, }, + [17] = { 0x10, 15, 3, }, + [18] = { 0x00, 27, 3, }, + [19] = { 0x00, 27, 3, }, + [20] = { 0x00, 27, 3, }, + [21] = { 0x00, 27, 3, }, + [22] = { 0x00, 0, 3, }, + [23] = { 0x00, 3, 3, }, + [24] = { 0x00, 6, 3, }, + [25] = { 0x20, 6, 3, }, + [26] = { 0x20, 6, 3, }, + [27] = { 0x20, 6, 3, }, + [28] = { 0x20, 9, 3, }, + [29] = { 0x20, 3, 3, }, + [30] = { 0x20, 6, 3, }, + [31] = { 0x20, 12, 3, }, + [32] = { 0x20, 12, 3, }, + [33] = { 0x20, 15, 3, }, + [34] = { 0x20, 15, 3, }, + [35] = { 0x20, 12, 3, }, + [36] = { 0x20, 15, 3, }, + [37] = { 0x10, 27, 3, }, + [38] = { 0x10, 18, 3, }, + [39] = { 0x10, 21, 3, }, + [40] = { 0x10, 24, 3, }, + [41] = { 0x20, 0, 3, }, + [42] = { 0x20, 18, 3, }, + [43] = { 0x20, 18, 3, }, + [44] = { 0x20, 18, 3, }, + [45] = { 0x20, 21, 3, }, + [46] = { 0x10, 15, 3, }, + [47] = { 0x20, 3, 3, }, + [48] = { 0x20, 3, 3, }, + [49] = { 0x20, 3, 3, }, + [50] = { 0x00, 6, 3, }, + [51] = { 0x00, 3, 3, }, + [52] = { 0x00, 0, 3, }, + [53] = { 0x00, 9, 3, }, + [54] = { 0x00, 12, 3, }, + [55] = { 0x20, 27, 3, }, + [56] = { 0x30, 6, 3, }, + [57] = { 0x30, 9, 3, }, + [58] = { 0x30, 15, 3, }, + [59] = { 0x30, 0, 3, }, + [60] = { 0x30, 9, 3, }, + [61] = { 0x30, 3, 3, }, + [62] = { 0x30, 12, 3, }, + [63] = { 0x30, 12, 3, }, + [64] = { 0x30, 18, 3, }, + [65] = { 0x10, 0, 3, }, + [66] = { 0x10, 6, 3, }, + [67] = { 0x10, 3, 3, }, + [68] = { 0x10, 9, 3, }, + [69] = { 0x30, 18, 3, }, + [70] = { 0x30, 15, 3, }, + [71] = { 0x40, 0, 3, }, + [72] = { 0x30, 27, 3, }, + [73] = { 0x30, 21, 3, }, + [74] = { 0x30, 24, 3, }, + [75] = { 0x40, 6, 3, }, + [76] = { 0x40, 3, 3, }, + [77] = { 0x40, 12, 3, }, + [78] = { 0x40, 9, 3, }, + [79] = { 0x10, 15, 3, }, + [80] = { 0x10, 12, 3, }, + [81] = { 0x10, 21, 3, }, + [82] = { 0x10, 18, 3, }, + [83] = { 0x30, 0, 3, }, + [84] = { 0x20, 27, 3, }, + [85] = { 0x30, 0, 3, }, + [86] = { 0x20, 6, 3, }, + [87] = { 0x20, 6, 3, }, + [88] = { 0x20, 6, 3, }, + [89] = { 0x20, 6, 3, }, + [90] = { 0x30, 0, 3, }, + [91] = { 0x30, 0, 3, }, + [92] = { 0x20, 9, 3, }, + [93] = { 0x20, 9, 3, }, + [94] = { 0x20, 9, 3, }, + [95] = { 0x20, 9, 3, }, + [96] = { 0x20, 21, 3, }, + [97] = { 0x20, 21, 3, }, + [98] = { 0x20, 24, 3, }, + [99] = { 0x20, 21, 3, }, + [100] = { 0x30, 6, 3, }, + [101] = { 0x00, 0, 3, }, + [102] = { 0x00, 15, 3, }, + [103] = { 0x00, 9, 3, }, + [104] = { 0x00, 12, 3, }, + [105] = { 0x00, 3, 3, }, + [106] = { 0x00, 6, 3, }, + [107] = { 0x20, 6, 3, }, + [108] = { 0x20, 6, 3, }, + [109] = { 0x20, 6, 3, }, + [110] = { 0x20, 6, 3, }, + [111] = { 0x20, 15, 3, }, + [112] = { 0x20, 15, 3, }, + [113] = { 0x20, 15, 3, }, + [114] = { 0x20, 12, 3, }, + [115] = { 0x20, 12, 3, }, + [116] = { 0x20, 12, 3, }, + [117] = { 0x20, 12, 3, }, + [118] = { 0x20, 12, 3, }, + [119] = { 0x20, 15, 3, }, + [120] = { 0x20, 18, 3, }, + [121] = { 0x10, 3, 3, }, + [122] = { 0x10, 12, 3, }, + [123] = { 0x10, 9, 3, }, + [124] = { 0x10, 6, 3, }, + [125] = { 0x20, 24, 3, }, + [126] = { 0x20, 24, 3, }, + [127] = { 0x20, 24, 3, }, + [128] = { 0x20, 27, 3, }, + [129] = { 0x20, 27, 3, }, + [130] = { 0x20, 27, 3, }, + [131] = { 0x00, 0, 3, }, + [132] = { 0x00, 15, 3, }, + [133] = { 0x00, 18, 3, }, + [134] = { 0x00, 21, 3, }, + [135] = { 0x20, 15, 3, }, + [136] = { 0x20, 18, 3, }, + [137] = { 0x20, 18, 3, }, + [138] = { 0x20, 18, 3, }, + [139] = { 0x20, 18, 3, }, + [140] = { 0x20, 21, 3, }, + [141] = { 0x20, 21, 3, }, + [142] = { 0x20, 21, 3, }, + [143] = { 0x00, 3, 3, }, + [144] = { 0x00, 6, 3, }, + [145] = { 0x00, 9, 3, }, + [146] = { 0x00, 12, 3, }, + [147] = { 0x20, 21, 3, }, + [148] = { 0x20, 24, 3, }, + [149] = { 0x20, 24, 3, }, + [150] = { 0x20, 24, 3, }, + [151] = { 0x10, 15, 3, }, + [152] = { 0x10, 12, 3, }, + [153] = { 0x10, 9, 3, }, + [154] = { 0x10, 6, 3, }, + [155] = { 0x10, 21, 3, }, + [156] = { 0x00, 21, 3, }, + [157] = { 0x00, 18, 3, }, + [158] = { 0x10, 3, 3, }, + [159] = { 0x10, 0, 3, }, + [160] = { 0x00, 27, 3, }, + [161] = { 0x00, 24, 3, }, + [162] = { 0x10, 18, 3, }, + [163] = { 0x00, 12, 3, }, + [164] = { 0x00, 9, 3, }, + [165] = { 0x00, 15, 3, }, + [166] = { 0x00, 18, 3, }, + [167] = { 0x00, 21, 3, }, + [168] = { 0x00, 24, 3, }, + [169] = { 0x00, 18, 3, }, + [170] = { 0x00, 15, 3, }, + [171] = { 0x00, 21, 3, }, + [172] = { 0x00, 24, 3, }, + [173] = { 0x00, 27, 3, }, + [174] = { 0x10, 0, 3, }, + [175] = { 0x30, 3, 3, }, + [176] = { 0x30, 3, 3, }, +}; + +_Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM, + "gpio_driving_info array size not match"); + +/* Unimplemented GPIOs are intentionally omitted here with width=0 */ +static const struct gpio_drv_info gpio_driving_adv_info[] = { + [53] = { 0x20, 0, 3, }, + [54] = { 0x20, 3, 3, }, + [55] = { 0x60, 0, 3, }, + [56] = { 0x60, 9, 3, }, + [57] = { 0x50, 0, 3, }, + [58] = { 0x50, 6, 3, }, + [59] = { 0x60, 3, 3, }, + [60] = { 0x60, 12, 3, }, + [61] = { 0x60, 6, 3, }, + [62] = { 0x60, 15, 3, }, + [63] = { 0x50, 3, 3, }, + [64] = { 0x50, 9, 3, }, + [65] = { 0x30, 0, 3, }, + [66] = { 0x30, 6, 3, }, + [67] = { 0x30, 3, 3, }, + [68] = { 0x30, 9, 3, }, + [175] = { 0x50, 12, 3, }, + [176] = { 0x50, 15, 3, }, +}; + void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; @@ -31,3 +252,29 @@ return reg_addr; } + +const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) +{ + if (ENV_BOOTBLOCK) { + uint32_t id = raw_id - SPI_AP_GPIO_BASE; + + if (id >= ARRAY_SIZE(bootblock_gpio_driving_info)) + return NULL; + return &bootblock_gpio_driving_info[id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_info)) + return NULL; + return &gpio_driving_info[raw_id]; + } +} + +const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) +{ + if (ENV_BOOTBLOCK) { + return NULL; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + return NULL; + return &gpio_driving_adv_info[raw_id]; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Gerrit-Change-Number: 74063 Gerrit-PatchSet: 10 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74062 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... soc/mediatek/mt8186: Reduce GPIO code size in bootblock Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downsized from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74062 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 127 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index f0cbb04..993dbe6 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -34,7 +34,7 @@ }; struct gpio_drv_info { - uint32_t offset; + uint8_t offset; uint8_t shift; uint8_t width; }; diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c index 5914346..0dad342 100644 --- a/src/soc/mediatek/mt8186/gpio.c +++ b/src/soc/mediatek/mt8186/gpio.c @@ -5,9 +5,34 @@ * Chapter number: 5.1 */ +#include <assert.h> #include <device/mmio.h> #include <gpio.h> +enum { + SPI0_CLK_A = 0, + SPI0_CSB_A = 1, + SPI0_MO_A = 2, + SPI0_MI_A = 3, + TDM_RX_BCK = 4, + TDM_RX_MCLK = 5, + TDM_RX_DATA0 = 6, + TDM_RX_DATA1 = 7, +}; + +static const struct gpio_drv_info bootblock_gpio_driving_info[] = { + /* GPIO 36~39 */ + [SPI0_CLK_A] = { 0x0, 9, 3, }, + [SPI0_CSB_A] = { 0x0, 9, 3, }, + [SPI0_MO_A] = { 0x0, 12, 3, }, + [SPI0_MI_A] = { 0x0, 9, 3, }, + /* GPIO 61~64 */ + [TDM_RX_BCK] = { 0x0, 24, 3, }, + [TDM_RX_MCLK] = { 0x0, 24, 3, }, + [TDM_RX_DATA0] = { 0x0, 24, 3, }, + [TDM_RX_DATA1] = { 0x0, 27, 3, }, +}; + static const struct gpio_drv_info gpio_driving_info[] = { [0] = { 0x0, 27, 3, }, [1] = { 0x0, 27, 3, }, @@ -253,6 +278,60 @@ return reg_addr; } +static const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) +{ + if (ENV_BOOTBLOCK) { + uint32_t id; + + switch (raw_id) { + case GPIO_ID(SPI0_CLK): + id = SPI0_CLK_A; + break; + case GPIO_ID(SPI0_CSB): + id = SPI0_CSB_A; + break; + case GPIO_ID(SPI0_MO): + id = SPI0_MO_A; + break; + case GPIO_ID(SPI0_MI): + id = SPI0_MI_A; + break; + case GPIO_ID(TDM_RX_BCK): + id = TDM_RX_BCK; + break; + case GPIO_ID(TDM_RX_MCLK): + id = TDM_RX_MCLK; + break; + case GPIO_ID(TDM_RX_DATA0): + id = TDM_RX_DATA0; + break; + case GPIO_ID(TDM_RX_DATA1): + id = TDM_RX_DATA1; + break; + default: + return NULL; + } + + assert(id < ARRAY_SIZE(bootblock_gpio_driving_info)); + return &bootblock_gpio_driving_info[id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_info)) + return NULL; + return &gpio_driving_info[raw_id]; + } +} + +static const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) +{ + if (ENV_BOOTBLOCK) { + return NULL; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + return NULL; + return &gpio_driving_adv_info[raw_id]; + } +} + static inline bool is_valid_drv(uint8_t drv) { return drv <= GPIO_DRV_16_MA; @@ -266,16 +345,16 @@ int gpio_set_driving(gpio_t gpio, uint8_t drv) { uint32_t mask; - const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; - const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; - void *reg, *reg_adv; + const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); + void *reg, *reg_adv, *reg_addr; + + if (!info) + return -1; if (!is_valid_drv(drv)) return -1; - reg = gpio_find_reg_addr(gpio) + info->offset; - reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; - if (info->width == 0) return -1; @@ -284,20 +363,27 @@ if ((uint32_t)drv > mask) return -1; + reg_addr = gpio_find_reg_addr(gpio); + reg = reg_addr + info->offset; clrsetbits32(reg, mask << info->shift, drv << info->shift); /* Disable EH if supported */ - if (adv_info->width != 0) + if (adv_info && adv_info->width != 0) { + reg_adv = reg_addr + adv_info->offset; clrbits32(reg_adv, BIT(adv_info->shift)); + } return 0; } int gpio_get_driving(gpio_t gpio) { - const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; + const struct gpio_drv_info *info = get_gpio_driving_info(gpio.id); void *reg; + if (!info) + return -1; + reg = gpio_find_reg_addr(gpio) + info->offset; if (info->width == 0) return -1; @@ -308,9 +394,12 @@ int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv) { uint32_t mask; - const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); void *reg_adv; + if (!adv_info) + return -1; + if (!is_valid_drv_adv(drv)) return -1; @@ -334,10 +423,13 @@ int gpio_get_driving_adv(gpio_t gpio) { - const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + const struct gpio_drv_info *adv_info = get_gpio_driving_adv_info(gpio.id); void *reg_adv; uint32_t drv; + if (!adv_info) + return -1; + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; if (adv_info->width == 0) return -1; diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index 8a1c147..1377e01 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -31,6 +31,8 @@ GPIO_DRV_16_MA = 7, }; +#define GPIO_ID(name) PAD_##name##_ID + #define PIN(id, name, flag, bit, base, offset, \ func1, func2, func3, func4, func5, func6, func7) \ PAD_##name##_ID = id, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 7 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytes
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74061 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytes ...................................................................... soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytes Original lastbus configuration consumes constant memory size by allocating 16 and 8 members arrays and the utilization is bad. Refactor the lastbus structs to save memory usage. BRANCH=none BUG=none TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes. Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74061 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/lastbus_v2.h M src/soc/mediatek/mt8188/lastbus.c 2 files changed, 100 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/lastbus_v2.h b/src/soc/mediatek/common/include/soc/lastbus_v2.h index d58da76..8146deb 100644 --- a/src/soc/mediatek/common/include/soc/lastbus_v2.h +++ b/src/soc/mediatek/common/include/soc/lastbus_v2.h @@ -3,8 +3,6 @@ #ifndef SOC_MEDIATEK_COMMON_LASTBUS_V2_H #define SOC_MEDIATEK_COMMON_LASTBUS_V2_H -#define NR_MAX_LASTBUS_IDLE_MASK 8 -#define NR_MAX_LASTBUS_MONITOR 16 #define TIMEOUT_THRES_SHIFT 16 #define TIMEOUT_TYPE_SHIFT 1 #define LASTBUS_TIMEOUT_CLR 0x0200 @@ -23,7 +21,7 @@ size_t num_ports; u16 bus_freq_mhz; size_t num_idle_mask; - struct lastbus_idle_mask idle_masks[NR_MAX_LASTBUS_IDLE_MASK]; + const struct lastbus_idle_mask *idle_masks; }; struct lastbus_config { @@ -31,7 +29,7 @@ unsigned int timeout_ms; unsigned int timeout_type; unsigned int num_used_monitors; - struct lastbus_monitor monitors[NR_MAX_LASTBUS_MONITOR]; + const struct lastbus_monitor *monitors; }; void lastbus_init(void); diff --git a/src/soc/mediatek/mt8188/lastbus.c b/src/soc/mediatek/mt8188/lastbus.c index f2c0b0d..5d117af 100644 --- a/src/soc/mediatek/mt8188/lastbus.c +++ b/src/soc/mediatek/mt8188/lastbus.c @@ -5,75 +5,83 @@ #include <soc/addressmap.h> #include <soc/lastbus_v2.h> +static const struct lastbus_idle_mask infra_ao_mask[] = { + { + .reg_offset = 0x04, + .reg_value = 0x2, + }, + { + .reg_offset = 0x08, + .reg_value = 0x10000, + }, +}; + +static const struct lastbus_idle_mask peri_ao_mask[] = { + { + .reg_offset = 0x04, + .reg_value = 0x20000, + }, +}; + +static const struct lastbus_idle_mask fmem_ao_mask[] = { + { + .reg_offset = 0x14, + .reg_value = 0x204, + }, +}; + +static const struct lastbus_monitor monitors[] = { + { + .name = "debug_ctrl_ao_INFRA_AO", + .base = INFRA_AO_DBUG_BASE, + .num_ports = 34, + .num_idle_mask = ARRAY_SIZE(infra_ao_mask), + .idle_masks = infra_ao_mask, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_INFRA2_AO", + .base = INFRA2_AO_DBUG_BASE, + .num_ports = 9, + .num_idle_mask = 0, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_PERI_AO", + .base = PERI_AO_BASE, + .num_ports = 25, + .num_idle_mask = ARRAY_SIZE(peri_ao_mask), + .idle_masks = peri_ao_mask, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_PERI_AO2", + .base = PERI_AO2_BASE, + .num_ports = 20, + .num_idle_mask = 0, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_PERI_PAR_AO", + .base = PERI_PAR_AO_BASE, + .num_ports = 18, + .num_idle_mask = 0, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_FMEM_AO", + .base = FMEM_AO_BASE, + .num_ports = 28, + .num_idle_mask = ARRAY_SIZE(fmem_ao_mask), + .idle_masks = fmem_ao_mask, + .bus_freq_mhz = 78, + }, +}; + const struct lastbus_config lastbus_cfg = { .latch_platform = "MT8188", .timeout_ms = 200, .timeout_type = 0, - .num_used_monitors = 6, - .monitors = { - { - .name = "debug_ctrl_ao_INFRA_AO", - .base = INFRA_AO_DBUG_BASE, - .num_ports = 34, - .num_idle_mask = 2, - .idle_masks = { - { - .reg_offset = 0x04, - .reg_value = 0x2, - }, - { - .reg_offset = 0x08, - .reg_value = 0x10000, - }, - }, - .bus_freq_mhz = 78, - }, - { - .name = "debug_ctrl_ao_INFRA2_AO", - .base = INFRA2_AO_DBUG_BASE, - .num_ports = 9, - .num_idle_mask = 0, - .bus_freq_mhz = 78, - }, - { - .name = "debug_ctrl_ao_PERI_AO", - .base = PERI_AO_BASE, - .num_ports = 25, - .num_idle_mask = 1, - .idle_masks = { - { - .reg_offset = 0x04, - .reg_value = 0x20000, - }, - }, - .bus_freq_mhz = 78, - }, - { - .name = "debug_ctrl_ao_PERI_AO2", - .base = PERI_AO2_BASE, - .num_ports = 20, - .num_idle_mask = 0, - .bus_freq_mhz = 78, - }, - { - .name = "debug_ctrl_ao_PERI_PAR_AO", - .base = PERI_PAR_AO_BASE, - .num_ports = 18, - .num_idle_mask = 0, - .bus_freq_mhz = 78, - }, - { - .name = "debug_ctrl_ao_FMEM_AO", - .base = FMEM_AO_BASE, - .num_ports = 28, - .num_idle_mask = 1, - .idle_masks = { - { - .reg_offset = 0x14, - .reg_value = 0x204, - }, - }, - .bus_freq_mhz = 78, - }, - }, + .num_used_monitors = ARRAY_SIZE(monitors), + .monitors = monitors, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe Gerrit-Change-Number: 74061 Gerrit-PatchSet: 4 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by Rex-BC Chen (Code Review) 10 Apr '23

10 Apr '23

Rex-BC Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel Geralt uses Samsung panel, and Mutto is responsible for bonding the panel and touch, so rename the panel description. Add power-on sequence for Samsung ATNA33XC20 panel. EDID Info: header: 00 ff ff ff ff ff ff 00 serial number: 4c 83 62 41 00 00 00 00 28 1e version: 01 04 basic params: b5 1d 11 78 02 chroma info: 0c f1 ae 52 3c b9 23 0c 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 2: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 3: 00 00 00 0f 00 d1 09 3c d1 09 3c 28 80 00 00 00 00 00 descriptor 4: 00 00 00 fe 00 41 54 4e 41 33 33 58 43 32 30 2d 30 20 extensions: 01 checksum: 6f BUG=b:276097739 TEST=test firmware display pass. Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74115 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/geralt/panel_geralt.c 1 file changed, 48 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve jason-ch chen: Looks good to me, but someone else must approve cong yang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 1cb8e47..159bc76 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -22,9 +22,9 @@ gpio_output(GPIO_MIPI_BL_PWM_1V8, 0); } -static void configure_edp_aux_backlight(void) +static void configure_edp_backlight(void) { - /* TODO: Add edp aux backlight for MUTTO_B152731E1 when we get MUTTO_B152731E1 */ + gpio_output(GPIO_AP_DISP_BKLTEN, 0); } static void power_on_mipi_boe_tv110c9m_ll0(void) @@ -48,9 +48,11 @@ mdelay(6); } -static void power_on_edp_mutto_b152731e1(void) +static void power_on_edp_samsung_atana33xc20(void) { - /* TODO: Add the poweron for MUTTO_B152731E1 when we get MUTTO_B152731E1 */ + gpio_output(GPIO_EN_PP3300_EDP_DISP_X, 1); + gpio_set_pull(GPIO_EDP_HPD_1V8, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode(GPIO_EDP_HPD_1V8, 4); } static struct panel_description panels[] = { @@ -62,9 +64,9 @@ .pwm_ctrl_gpio = true, }, [11] = { - .name = "MUTTO_B152731E1", - .power_on = power_on_edp_mutto_b152731e1, - .configure_panel_backlight = configure_edp_aux_backlight, + .name = "SAMSUNG_ATANA33XC20", + .power_on = power_on_edp_samsung_atana33xc20, + .configure_panel_backlight = configure_edp_backlight, .disp_path = DISP_PATH_EDP, .pwm_ctrl_gpio = false, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 14 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Build for chromeOS
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74097 ) Change subject: mb/google/myst: Build for chromeOS ...................................................................... mb/google/myst: Build for chromeOS Adjust build configs to build Myst for chromeOS. BUG=b:270618097 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Reviewed-on: https://review.coreboot.org/c/coreboot/+/74097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/Makefile.inc 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index d8be3b8..b9e87fb 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select MAINBOARD_HAS_CHROMEOS select SOC_AMD_PHOENIX config DEVICETREE @@ -26,4 +27,9 @@ config MAINBOARD_PART_NUMBER default "Myst" if BOARD_GOOGLE_MYST +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + endif # BOARD_GOOGLE_BASEBOARD_MYST diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc index 0315ba9..5bd6aca 100644 --- a/src/mainboard/google/myst/Makefile.inc +++ b/src/mainboard/google/myst/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += mainboard.c ramstage-y += port_descriptors.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard -- To view, visit https://review.coreboot.org/c/coreboot/+/74097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Gerrit-Change-Number: 74097 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
by Dtrain Hsu (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Derek Huang, Kapil Porwal. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74246 ) Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi Reviewer Would you help to review this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/74246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Gerrit-Change-Number: 74246 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ron Lee <ron.lee(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 01:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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