coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: include/option.h: Implement no-op option API for SMM
by Benjamin Doron (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Arthur Heymans, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73906 ) Change subject: include/option.h: Implement no-op option API for SMM ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: If this is desired, resolve the function redefinition by *conditionally* compiling all option API implementations into SMM. -- To view, visit https://review.coreboot.org/c/coreboot/+/73906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f830f08ba42bd8e8cf1961ca83673a52be9460 Gerrit-Change-Number: 73906 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 09 Apr 2023 20:46:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: include/option.h: Implement no-op option API for SMM
by Benjamin Doron (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Arthur Heymans, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73906 ) Change subject: include/option.h: Implement no-op option API for SMM ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/73906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f830f08ba42bd8e8cf1961ca83673a52be9460 Gerrit-Change-Number: 73906 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 09 Apr 2023 20:38:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: drivers/efi: Fix linker error when SMM phase uses option API
by Benjamin Doron (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Arthur Heymans, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73905 ) Change subject: drivers/efi: Fix linker error when SMM phase uses option API ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/73905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3b52965d8fde141c12266a716f254dd45559d5 Gerrit-Change-Number: 73905 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 09 Apr 2023 19:59:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Matt DeVillier (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74288 to look at the new patch set (#3). Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... soc/amd/common/blk/pcie: Program LTR max latencies PCIe bridges need to provide the LTR (latency tolernace reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.047ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Matt DeVillier (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74288 to look at the new patch set (#2). Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... soc/amd/common/blk/pcie: Program LTR max latencies PCIe bridges need to provide the LTR (latency tolernace reporting) maximum snoop/non-snoop values so that they are inherited by downstream PCIe devices which support and enable LTR. Without this, downstream devices cannot have LTR enabled, which is a requirement for supporting PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior, including some devices refusing to enter L1 low power modes at all. Program the max snoop/non-snoop latency values for all PCIe bridges using the same value used by AGESA/FSP, 1.047ms. BUG=b:265890321 TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure LTR is enabled, latency values are correctly set, and that device power draw at idle is in the expected range (<25 mW). Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Matt DeVillier (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 ) Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/pci/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/74288/comment/e056f653_798a33fc PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US > How was this value determined? value used by AGESA/FSP (and has been unchanged for 5 years per commit history), I'll update the commit msg with that info -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 09 Apr 2023 19:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
by Kyösti Mälkki (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74316 ) Change subject: sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC ...................................................................... sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Following boards are excluded from the change at this time: aopen/dxplplusu, emulation/qemu-i440fx,qemu-q35 Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/madt.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/Kconfig 29 files changed, 35 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/74316/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index ec7fcc4..5af8b22 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -31,6 +31,9 @@ Set to indicate <soc/nvs.h> exists for the platform with a definition for global_nvs. +config ACPI_COMMON_MADT_LAPIC + bool + config ACPI_NO_MADT bool help diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 9c67fd3..b61b84f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -293,6 +293,9 @@ if (CONFIG(ACPI_HAVE_PCAT_8259)) madt->flags |= 1; + if (CONFIG(ACPI_COMMON_MADT_LAPIC)) + current = acpi_create_madt_lapics_with_nmis(current); + if (!CONFIG(ACPI_NO_MADT)) current = acpi_fill_madt(current); diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index 1cf7e74..87941fa 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index b8ac827..08effca 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -21,9 +21,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index fd62ad6..289efbc 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -2,6 +2,7 @@ bool depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_COMMON_MADT_LAPIC help Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 49fb658..cb8039d 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -24,9 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 83b24ec..17d8955 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -23,9 +23,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 8e90d44..5e37a27 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -24,9 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a6f1ebd..227a5d8 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -28,9 +28,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index caa6496..947c806 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,9 +26,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* create all subtables for processors */ - current = acpi_create_madt_lapics_with_nmis(current); - /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5ecfe3e..0f908b6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 75c2863..4d5b5c2 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -87,9 +87,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4d3d4df..8d540f3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 46a8771..6ea1039 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -328,9 +328,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 5a80d32..63f0439 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -4,6 +4,7 @@ config PCH_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index bf5fa56..8f4e308 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_ACPI depends on SOC_INTEL_COMMON_BLOCK_CPU depends on SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID bool help Intel Processor common code for ACPI diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4b790b7..50b4573 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -87,11 +87,8 @@ size_t ioapic_entries; /* Local APICs */ - - if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + if (!CONFIG(ACPI_COMMON_MADT_LAPIC)) current = acpi_create_madt_lapics_with_nmis_hybrid(current); - else - current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ ioapic_entries = soc_get_ioapic_info(&ioapic_table); diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 53f7b3e..4b19431 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7fee1f1..a0d8605 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -10,6 +10,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index b85e110..2482391 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index b1b885b..330915f 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 69c1469..2871453 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -351,9 +351,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 4d6b097..d93afa6 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c index 009c9ea..1ac8149 100644 --- a/src/southbridge/intel/i82801ix/madt.c +++ b/src/southbridge/intel/i82801ix/madt.c @@ -6,9 +6,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b189852..62684ec 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ead2b8a..8ff7926 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -381,9 +381,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index fd5e322..ffeef5d 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 26b1630..c5b1f0b 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -8,9 +8,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Local APICs */ - current = acpi_create_madt_lapics_with_nmis(current); - /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 6305812..9cea74b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT -- To view, visit https://review.coreboot.org/c/coreboot/+/74316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Gerrit-Change-Number: 74316 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPICs
by Kyösti Mälkki (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Lance Zhao, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Sridhar Siricilla, Arthur Heymans, Ronak Kanabar, Tim Chu. Hello Lance Zhao, build bot (Jenkins), Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Sridhar Siricilla, Arthur Heymans, Ronak Kanabar, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74312 to look at the new patch set (#2). Change subject: ACPI: Add helper for MADT LAPICs ...................................................................... ACPI: Add helper for MADT LAPICs This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 4 files changed, 33 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74312/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592c69e0f52687924fe41189b082c86913999136 Gerrit-Change-Number: 74312 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: AMD binaryPI: Declare IOAPIC IDs
by Kyösti Mälkki (Code Review) 09 Apr '23

09 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74315 ) Change subject: AMD binaryPI: Declare IOAPIC IDs ...................................................................... AMD binaryPI: Declare IOAPIC IDs There is no longer a relation between MAX_CPUS and IOAPIC IDs, start the cleanup with new declarations. Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/00730F01/state_machine.c A src/southbridge/amd/pi/hudson/ioapic.h M src/southbridge/amd/pi/hudson/sm.c 5 files changed, 35 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/74315/1 diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index d786215..bc5ff64 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -10,11 +11,11 @@ current = acpi_create_madt_lapics(current); /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID, IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID, IO_APIC2_ADDR, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index dab0e72..644e2d5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -23,6 +23,7 @@ #include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/pi/hudson/ioapic.h> #include <amdblocks/cpu.h> #define MAX_NODE_NUMS MAX_NODES @@ -221,7 +222,7 @@ static void northbridge_init(struct device *dev) { - setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1); + setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -253,7 +254,7 @@ ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->handle = FCH_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); @@ -263,7 +264,7 @@ ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->dte_setting = 0x00; - ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->handle = GNB_IOAPIC_ID; ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index ba34dab..0693a5d 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -9,6 +9,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/nb_common.h> +#include <southbridge/amd/pi/hudson/ioapic.h> void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -64,8 +65,8 @@ * when IOMMU build config is enabled otherwise AGESA will skip * it during IOMMU init and IVRS generation. */ - Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID; + Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID; } /* Code for creating CDIT requires hop count table. If it is not diff --git a/src/southbridge/amd/pi/hudson/ioapic.h b/src/southbridge/amd/pi/hudson/ioapic.h new file mode 100644 index 0000000..757e5c8 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/ioapic.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_IOAPIC_H +#define AMD_BLOCK_IOAPIC_H + +/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */ +#define FCH_IOAPIC_ID (CONFIG_MAX_CPUS) +#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1) + +#endif /* AMD_BLOCK_IOAPIC_H */ diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 79d1005..c40bf5e 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> #include <device/smbus.h> #include <arch/ioapic.h> +#include <southbridge/amd/pi/hudson/ioapic.h> #include "hudson.h" #include "smbus.c" @@ -21,7 +22,7 @@ static void sm_init(struct device *dev) { - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID); } static int lsmbus_recv_byte(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/74315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Gerrit-Change-Number: 74315 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/amd: Clarify ACPI _PRT entry generation
by Kyösti Mälkki (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74314 ) Change subject: soc/amd: Clarify ACPI _PRT entry generation ...................................................................... soc/amd: Clarify ACPI _PRT entry generation The reference to a constant FCH IOAPIC interrupt count used with GNB IOAPIC was a bit obscure. Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/ioapic.h M src/soc/amd/common/block/pci/acpi_prt.c 2 files changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74314/1 diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index a91ac14..6c5282b 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -5,7 +5,6 @@ #define IO_APIC_ADDR 0xfec00000 #define VIO_APIC_VADDR ((u8 *)IO_APIC_ADDR) -#define IO_APIC_INTERRUPTS 24 #ifndef __ACPI__ diff --git a/src/soc/amd/common/block/pci/acpi_prt.c b/src/soc/amd/common/block/pci/acpi_prt.c index c142f57..f748024 100644 --- a/src/soc/amd/common/block/pci/acpi_prt.c +++ b/src/soc/amd/common/block/pci/acpi_prt.c @@ -7,20 +7,22 @@ #include <arch/ioapic.h> #include <device/device.h> +/* GNB IO-APIC is located after the FCH IO-APIC */ +#define FCH_IOAPIC_INTERRUPTS 24 +#define GNB_GSI_BASE FCH_IOAPIC_INTERRUPTS + static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) { unsigned int irq; acpigen_write_package(4); /* Package - APIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - /* GNB IO-APIC is located after the FCH IO-APIC */ - irq = IO_APIC_INTERRUPTS; - irq += pci_calculate_irq(routing_info, i); + irq = pci_calculate_irq(routing_info, i); acpigen_write_PRT_GSI_entry( 0, /* There is only one device attached to the bridge */ i, /* pin */ - irq); + GNB_GSI_BASE + irq); } acpigen_pop_len(); /* Package - APIC Routing */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/74314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Gerrit-Change-Number: 74314 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023