coreboot-gerrit April 2023

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[M] Change in coreboot[master]: ACPI: Add helper for MADT LAPICs
by Kyösti Mälkki (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Lance Zhao, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74312 ) Change subject: ACPI: Add helper for MADT LAPICs ...................................................................... ACPI: Add helper for MADT LAPICs This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 4 files changed, 31 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74312/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2439d7b..0549c0b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -122,7 +122,7 @@ return sizeof(acpi_mcfg_mmconfig_t); } -int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) +static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) { lapic->type = LOCAL_APIC; /* Local APIC structure */ lapic->length = sizeof(acpi_madt_lapic_t); @@ -133,7 +133,7 @@ return lapic->length; } -int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic) +static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic) { lapic->type = LOCAL_X2APIC; /* Local APIC structure */ lapic->reserved = 0; @@ -145,6 +145,16 @@ return lapic->length; } +unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id) +{ + if (lapic_id < 0xff) + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index, lapic_id); + else + current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index, lapic_id); + + return current; +} + static unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; @@ -159,14 +169,8 @@ } if (num_cpus > 1) bubblesort(apic_ids, num_cpus, NUM_ASCENDING); - for (index = 0; index < num_cpus; index++) { - if (apic_ids[index] < 0xff) - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, apic_ids[index]); - else - current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, - index, apic_ids[index]); - } + for (index = 0; index < num_cpus; index++) + current = acpi_create_madt_one_lapic(current, index, apic_ids[index]); return current; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 36201ae..bfa111b 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1334,7 +1334,6 @@ int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target); -int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base); int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); @@ -1343,12 +1342,11 @@ void acpi_create_madt(acpi_madt_t *madt); +unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current); -int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); - int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 2e39f72..e18c288 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -81,14 +81,9 @@ { size_t index; - for (index = 0; index < cpu_apic_info.total_cpu_cnt; index++) { - if (cpu_apic_info.apic_ids[index] < 0xff) - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, cpu_apic_info.apic_ids[index]); - else - current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, - index, cpu_apic_info.apic_ids[index]); - } + for (index = 0; index < cpu_apic_info.total_cpu_cnt; index++) + current = acpi_create_madt_one_lapic(current, index, + cpu_apic_info.apic_ids[index]); return current; } diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 619e5bb..c609f4f 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -540,8 +540,7 @@ } if (!cpu->enabled) continue; - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, num_cpus, - cpu->path.apic.apic_id); + current = acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id); num_cpus++; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592c69e0f52687924fe41189b082c86913999136 Gerrit-Change-Number: 74312 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: ACPI: Add helper for MADT LAPIC NMIs
by Kyösti Mälkki (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74311 ) Change subject: ACPI: Add helper for MADT LAPIC NMIs ...................................................................... ACPI: Add helper for MADT LAPIC NMIs This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/cpu_hybrid.c 3 files changed, 28 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/74311/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 53b1607..2439d7b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -213,7 +213,7 @@ return irqoverride->length; } -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, +static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */ @@ -225,7 +225,7 @@ return lapic_nmi->length; } -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, +static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint) { lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */ @@ -240,12 +240,10 @@ return lapic_nmi->length; } -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +unsigned long acpi_create_madt_lapic_nmis(unsigned long current) { const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; - current = acpi_create_madt_lapics(current); - /* 1: LINT1 connect to NMI */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, @@ -258,6 +256,13 @@ return current; } +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +{ + current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapic_nmis(current); + return current; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e99f5b9..36201ae 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1340,14 +1340,15 @@ int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); + +unsigned long acpi_create_madt_lapic_nmis(unsigned long current); + int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); -int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint); + int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 7725e3f..2e39f72 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -95,19 +95,8 @@ unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current) { - const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; - current = acpi_create_madt_lapics_hybrid(current); - - /* 1: LINT1 connect to NMI */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); - - if (!CONFIG(XAPIC_ONLY)) - current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1); - + current = acpi_create_madt_lapic_nmis(current); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Gerrit-Change-Number: 74311 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: binaryPI: Use common code for LAPIC NMIs
by Kyösti Mälkki (Code Review) 08 Apr '23

08 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74310 ) Change subject: binaryPI: Use common code for LAPIC NMIs ...................................................................... binaryPI: Use common code for LAPIC NMIs Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/northbridge/amd/pi/00730F01/acpi_tables.c 3 files changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74310/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2706bf7..53b1607 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -145,7 +145,7 @@ return lapic->length; } -unsigned long acpi_create_madt_lapics(unsigned long current) +static unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; int index, apic_ids[CONFIG_MAX_CPUS] = {0}, num_cpus = 0; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index a108d6a..e99f5b9 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1343,7 +1343,7 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); -unsigned long acpi_create_madt_lapics(unsigned long current); + unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index d786215..1cf7e74 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -7,7 +7,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, @@ -26,9 +26,5 @@ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Gerrit-Change-Number: 74310 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: payloads/grub: Work around entry point issue
by Paul Menzel (Code Review) 08 Apr '23

08 Apr '23

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64235 ) Change subject: payloads/grub: Work around entry point issue ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: This makes the build fail with clang, as that does not seem to support that switch. clang: error: unknown argument: '-fno-reorder-functions' [A patch seems to be available since 2017.](https://reviews.llvm.org/D34796) -- To view, visit https://review.coreboot.org/c/coreboot/+/64235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a12f45d30b781870faa38575e8b2c10e0a42e8 Gerrit-Change-Number: 64235 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hackware <human(a)hackware.cl> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sat, 08 Apr 2023 09:37:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash
by Bao Zheng (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74260 to look at the new patch set (#6). Change subject: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash ...................................................................... soc/amd/spi: Add xlate_windows to mmap 32M/64M flash For the flash size bigger than 16M, AMD SOC maps only one 16M page at a time and use SPI ROM page register to switch pages. We use "translated region device" to let CBFS and flashmap access the physical SPI device not being aware the existence of the switcher. We need to switch back to page 0 in munmap because the FSP relies on this fact. This is one of series of patches to support 32/64M flash. The most important one. BUG=b:255374782 Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/spi_map_big.c 3 files changed, 254 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74260/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Nico Huber. Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: Just rebased on master and fixed merge conflicts -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 17 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 08 Apr 2023 08:01:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
by Sean Rhodes (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Felix Singer, Tarun Tuli, Subrata Banik, Christian Walter, Maximilian Brune, Angel Pons, Michael Niewöhner, Martin Roth, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73902 ) Change subject: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > > Isn't the only problem with the patch the "don't" in the help text? Surely it's easier to just rem […] Why not just go for a pragmatic approach and fix it? Reverting 4 patches to a state where acpi and devicetree are out of kilter, on the grounds the kconfig and device are - just seems silly to me... -- To view, visit https://review.coreboot.org/c/coreboot/+/73902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Gerrit-Change-Number: 73902 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 08 Apr 2023 07:59:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Nico Huber, Evgeny Zinoviev. Evgeny Zinoviev has uploaded a new patch set (#17) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Tested on ThinkPad X220 (i5-2520M) and ThinkPad W530 (i7-3940XM). Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.default M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.default M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.default M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.default M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 22 files changed, 123 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 17 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Sridhar Siricilla (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Dinesh Gehlot, Rizwan Qureshi, Reka Norman, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 18: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/74005/comment/5c933445_7f369142 PS18, Line 1226: .group_id = MKHI_GROUP_ID_GEN, : .command = MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO, > > Tried checking the bug before posting comments here. If possible, can you add me to the bug? […] Thanks Subrata for adding me to the bug. It looks the command number got changed from the initial patch to current one and command# GEN_GET_IMAGE_FW_VERSION was discussed in the bug, but here I see GET BOOT PARTITION INFO (which is meant to get CSE Lite RO/RW boot partitions versions and status). I am not sure why it got changed in patch#8! -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 18 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Sat, 08 Apr 2023 07:41:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
by Michael Niewöhner (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Felix Singer, Sean Rhodes, Tarun Tuli, Subrata Banik, Christian Walter, Maximilian Brune, Angel Pons, Martin Roth, Lean Sheng Tan. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73902 ) Change subject: Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: > Isn't the only problem with the patch the "don't" in the help text? Surely it's easier to just remove that. No, check CB:73903 for the main reasons, please. I've also added references to the various problems now. > For sure, there is a devicetree option but the point of this patch was to tie ACPI and FSP together to one Kconfig option However, this created a conflict. It's not a good idea to have both devicetree option AND Kconfig for the same thing File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/73902/comment/98226af7_28c1dc9e PS4, Line 325: params->D3HotEnable = !config->TcssD3HotDisable; : cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else : params->D3ColdEnable = !config->TcssD3ColdDisable; : for reference: https://review.coreboot.org/c/coreboot/+/72800/4/src/soc/intel/tigerlake/fs… -- To view, visit https://review.coreboot.org/c/coreboot/+/73902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Gerrit-Change-Number: 73902 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 08 Apr 2023 07:31:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: comment

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