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Utkarsh Verma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74170 )
Change subject: arch/x86/smbios: Fix file formatting
......................................................................
Patch Set 4:
(2 comments)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/74170/comment/9553d149_b9b0469c
PS2, Line 378:
: t->bios_characteristics = BIOS_CHARACTERISTICS_PCI_SUPPORTED
: | BIOS_CHARACTERISTICS_SELECTABLE_BOOT
: | BIOS_CHARACTERISTICS_UPGRADEABLE;
> Yes, but it was the result of the `.clang-format` file. […]
Fix in the new changes
https://review.coreboot.org/c/coreboot/+/74170/comment/72586f8a_e80eec0e
PS2, Line 1276: || device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
> What exactly is fixed here? Both conditions were nicely aligned before.
Fixed in the new changes.
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
......................................................................
soc/amd/common/blk/pcie: Program LTR max latencies
PCIe bridges need to provide the LTR (latency tolernace reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.
BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).
Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/pci/pcie_gpp.c
1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/1
diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c
index 0ce3268..5df1cb1 100644
--- a/src/soc/amd/common/block/pci/pcie_gpp.c
+++ b/src/soc/amd/common/block/pci/pcie_gpp.c
@@ -47,6 +47,20 @@
acpigen_pop_len(); /* Scope */
}
+/* Latency tolerance reporting, max snoop/non-snoop latency value 1.047ms */
+#define PCIE_LTR_MAX_LATENCY_1047US 0x1001
+
+static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop)
+{
+ *max_snoop = PCIE_LTR_MAX_LATENCY_1047US;
+ *max_nosnoop = PCIE_LTR_MAX_LATENCY_1047US;
+}
+
+static struct pci_operations pcie_ops = {
+ .get_ltr_max_latencies = pcie_get_ltr_max_latencies,
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
struct device_operations amd_internal_pcie_gpp_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
@@ -65,4 +79,5 @@
.reset_bus = pci_bus_reset,
.acpi_name = pcie_gpp_acpi_name,
.acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
+ .ops_pci = &pcie_ops,
};
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Change subject: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74249/comment/951b5363_4eb9038e
PS2, Line 10: to the only valid value and prevent mainboard overrides.
… by making the option non-user-configurable.
File src/soc/amd/phoenix/Kconfig:
https://review.coreboot.org/c/coreboot/+/74249/comment/c84db46a_0a879668
PS2, Line 310: Typically this is calculated by the ROM size, but there may
: be situations where you want to put the firmware directory
: table in a different location.
: 0: 512 KB - 0xFFFA0000
: 1: 1 MB - 0xFFF20000
: 2: 2 MB - 0xFFE20000
: 3: 4 MB - 0xFFC20000
: 4: 8 MB - 0xFF820000
: 5: 16 MB - 0xFF020000
Should this be updated too?
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Change subject: mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman
......................................................................
Patch Set 13:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69705/comment/504e305b_5aa6f794
PS13, Line 7: mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman
Maybe:
> mb/amd/birman: Update DXIO descripters per schematic
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Change subject: mb/amd/birman/ec.c: Update EC configuration for birman
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73971/comment/11ad4356_f3b49cbb
PS7, Line 7: Update EC configuration for birman
“for birman” is redundant. Maybe:
> Update EC configuration per schematic
File src/mainboard/amd/birman/ec.c:
https://review.coreboot.org/c/coreboot/+/73971/comment/c2806664_32692536
PS7, Line 219: for (i = 0; i < count; i++) {
Add a blank line above?
https://review.coreboot.org/c/coreboot/+/73971/comment/3258e6ad_315727a8
PS7, Line 222: cfg[i].addr, tmp);
Fits on the previous line?
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Change subject: mb/google/myst: Enable gfx_hda
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74278/comment/600aeeb6_aefaa469
PS4, Line 148: chip drivers/usb/acpi
Unrelated? (Rebase glitch?)
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Change subject: arch/arm* Fix some linter warnings and errors
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74173/comment/5d59eef9_9ff67928
PS1, Line 7: Fixed
> Fix linter warnings and errors […]
Done
https://review.coreboot.org/c/coreboot/+/74173/comment/007b777d_ada76c7e
PS1, Line 7: src/arch/ Fixed some linter warnings and errors
> Maybe split the commit into three: arch/arm*, arch/riscv, console.
Done, this is the first patch, two others will follow :)
https://review.coreboot.org/c/coreboot/+/74173/comment/c99e16c9_f7bf496e
PS1, Line 9: This is my first commit to coreboot, so please tell me if I'm missing something.
> > Possible unwrapped commit description (prefer a maximum 72 chars per line) […]
Done
https://review.coreboot.org/c/coreboot/+/74173/comment/5862c323_5920106f
PS1, Line 9: This is my first commit to coreboot, so please tell me if I'm missing something.
> Welcome to coreboot. This could be added as a comment, but does not belong into the commit message.
Done
Patchset:
PS2:
Thank you for your time and tips!
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/google/myst/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/74099/comment/bc2fd7b0_8c3ff575
PS18, Line 18: Name(LIDS, 0)
> https://review.coreboot. […]
Thank you. Maybe add a comment with to-do?
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Hello Felix Singer, build bot (Jenkins), Philipp Hug, Julius Werner, ron minnich, Elyes Haouas,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74173
to look at the new patch set (#2).
Change subject: arch/arm* Fix some linter warnings and errors
......................................................................
arch/arm* Fix some linter warnings and errors
Correct some linter issues.
Some changes seem like no big addition to readability to me,
but I guess having everything more uniform is good.
Signed-off-by: Philipp Macher <philipp-macher(a)web.de>
Change-Id: I976cffe971695f591ec42fce46e6743444277759
---
M src/arch/arm/include/arch/hlt.h
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm64/include/arch/hlt.h
3 files changed, 20 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74173/2
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 30:
(2 comments)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/0cad5ca3_748d85fb
PS30, Line 49: .gpio_group_id = GPIO_27,
> Similar to comment below. SD_AUX_RST is on GPIO_29.
Done
https://review.coreboot.org/c/coreboot/+/74112/comment/46c2f10e_9fdd6f58
PS30, Line 64: .gpio_group_id = GPIO_6,
> I'm not sure what this does, but on Skyrim GPIO_6 is tied to SSD_AUX_RST. […]
Done
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