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Change subject: mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman
......................................................................
mb/amd/birman/port_descriptors_phoenix.c: Update DXIO for birman
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B
v0.7
Update devicetree to reference the updated DXIO descriptors.
TEST=boot birman and note the devices show up in the logs correctly
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
---
M src/mainboard/amd/birman/devicetree_phoenix.cb
M src/mainboard/amd/birman/port_descriptors_phoenix.c
2 files changed, 187 insertions(+), 52 deletions(-)
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Change subject: mb/amd/birman/ec.c: Update EC configuration for birman
......................................................................
mb/amd/birman/ec.c: Update EC configuration for birman
Update the EC GPIO values for Birman, per schematic # 105-D67000-00B
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec
---
M src/mainboard/amd/birman/Kconfig
M src/mainboard/amd/birman/ec.c
2 files changed, 258 insertions(+), 40 deletions(-)
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72800 )
Change subject: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT
......................................................................
Patch Set 8:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/72800/comment/9688802e_e9f538f6
PS4, Line 1004: Don't support D3Cold"
: default n if NO_S0IX_SUPPORT
> Sheng, while I usually would agree fixing stuff instead of reverting, there are IMHO two strong argu […]
Michael,
1. Relevant reviewers have been added to the patch series and ample of time have been allowed for everyone to review this, hence their proper review process has been followed, please correct me if I am wrong.
2. It still does not justify a blanket revert, and in the past there were always miss like this, I would prefer to follow the same process to communicate with the patch submitter and come up with a proper fix.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73087 )
Change subject: mb/intel/dq67sw: Add LGA1155 microATX mainboard
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Thank you again for making this port, and also for [uploading the logs to the board status repository](https://review.coreboot.org/plugins/gitiles/board-status/+/a25a…. Three observations:
1. Despite `CONFIG_COMPRESSED_PAYLOAD_LZMA=y` the `cbfstool` output says, that [`fallback/payload` is not compressed](https://review.coreboot.org/plugins/gitiles/board-status/+/a25a…:
fallback/payload 0x440c0 simple elf 780146 none
2. With log level `SPEW` the CBMEM pre-console buffer is too small and might need to be increased for your board.
3. There are warnings about leftover static devices:
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:01.1
[WARN ] PCI: 00:01.2
[WARN ] PCI: 00:04.0
[WARN ] PCI: 00:06.0
[WARN ] PCI: 00:14.0
[WARN ] PCI: 00:16.1
[WARN ] PCI: 00:16.2
[WARN ] PCI: 00:16.3
[WARN ] PCI: 00:1c.1
[WARN ] PCI: 00:1c.2
[WARN ] PCI: 00:1c.3
[WARN ] PCI: 00:1c.7
[WARN ] PCI: Check your devicetree.cb.
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Change subject: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT
......................................................................
Patch Set 8:
(1 comment)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/72800/comment/35655312_527e77fb
PS4, Line 1004: Don't support D3Cold"
: default n if NO_S0IX_SUPPORT
> hi Michael, thanks for finding the bug/ error here. […]
Sheng, while I usually would agree fixing stuff instead of reverting, there are IMHO two strong arguments against, in that case:
1) Since there are more flaws in this series of changes, it's hard to believe for me that there was any proper review. Your statement regarding lack of review resources emphasizes this.
2) Due to the conflicts created, I fear these changes create some sort of chaos in the tree as soon as the options get used by other boards, making later cleanup a cumbersome process, as one has to be careful to not break any of these boards.
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 19:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173676):
https://review.coreboot.org/c/coreboot/+/74099/comment/2b8110e1_c15cb4a1
PS19, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173676):
https://review.coreboot.org/c/coreboot/+/74099/comment/4814d1f2_b17fc1a1
PS19, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Configure WLAN
......................................................................
mb/google/myst: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mapping derived from myst schematic.
BUG=b:275965982
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/bootblock.c
A src/mainboard/google/myst/romstage.c
M src/mainboard/google/myst/variants/baseboard/Makefile.inc
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/gpio.c
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
7 files changed, 104 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74113/30
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
mb/google/myst: Enable PCIe devices in devicetree
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/port_descriptors.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
3 files changed, 135 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/30
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Change subject: mb/google/myst: Add ACPI configuration for USB ports
......................................................................
mb/google/myst: Add ACPI configuration for USB ports
The USB port configuration was derived from the PPR and schematics.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras (World/User facing)
1 Bluetooth transceiver
1 WWAN
BUG=b:275905635
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Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
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---
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1 file changed, 98 insertions(+), 5 deletions(-)
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Change subject: mb/google/myst: Enable iommu
......................................................................
mb/google/myst: Enable iommu
Enable iommu in devicetree for myst in order to allow kernel to load and
initialize IOMMU.
Bug=b:276805280
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Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
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---
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