coreboot-gerrit April 2023

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[M] Change in coreboot[master]: Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik, Lean Sheng Tan, Felix Held. Hello build bot (Jenkins), Sean Rhodes, Tarun Tuli, Subrata Banik, Lean Sheng Tan, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/73901 to review the following change. Change subject: Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol" ...................................................................... Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol" This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4. Reason for revert: TBD; other revert depends on it Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/alderlake/acpi/tcss_dma.asl M src/soc/intel/alderlake/acpi/tcss_pcierp.asl M src/soc/intel/alderlake/acpi/tcss_xhci.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 10 files changed, 60 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/73901/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a8c9aeb..dd6bb22 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -328,6 +328,12 @@ int default 8 +config SOC_INTEL_ALDERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold. + config ENABLE_SATA_TEST_MODE bool "Enable test mode for SATA margining" default n diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 5c95997..1f626fc 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -583,7 +583,7 @@ } } -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -654,7 +654,7 @@ STAT = 0 } } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index ca47bd0..1483c0b 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,16 +28,16 @@ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x04) #else Return (0x03) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -49,12 +49,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -66,7 +66,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 6dbde46..4f1eec5 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -247,16 +247,16 @@ Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index ddc5a66..c0dc141 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 } /* @@ -43,7 +43,7 @@ */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { \_SB.PCI0.D3C }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 /* * XHCI controller _DSM method diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d4b16c0..788ee51 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -206,6 +206,12 @@ int default 6 +config SOC_INTEL_TIGERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold + config SOC_INTEL_UART_DEV_MAX int default 3 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 98337a3..be9d306 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -676,7 +676,7 @@ } } -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -787,7 +787,7 @@ STAT = 0 } } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 /* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index bbb0b6a..3c19ef6 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -27,11 +27,11 @@ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x04) #else Return (0x03) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } /* @@ -40,7 +40,7 @@ */ Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -52,12 +52,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -69,7 +69,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index a8e19ed..fda58e7 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -247,7 +247,7 @@ Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x4) #else Return (0x3) @@ -256,7 +256,7 @@ Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { \_SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index ddc5a66..a3b8c8f 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 } /* @@ -43,7 +43,7 @@ */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { \_SB.PCI0.D3C }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 /* * XHCI controller _DSM method -- To view, visit https://review.coreboot.org/c/coreboot/+/73901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 Gerrit-Change-Number: 73901 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/myst: Enable chromeOS EC
by Paul Menzel (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74099 ) Change subject: mb/google/myst: Enable chromeOS EC ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/myst/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74099/comment/0bc731a7_1e2bcb32 PS18, Line 18: Name(LIDS, 0) Why does this need to be written here, and is not part of the EC ASL files? Also only the AMD boards seem to this. Lastly, Please add a space before the (. -- To view, visit https://review.coreboot.org/c/coreboot/+/74099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Gerrit-Change-Number: 74099 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Sean Rhodes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72800 ) Change subject: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/72800/comment/fa128993_af52a718 PS4, Line 325: params->D3HotEnable = !config->TcssD3HotDisable; : : cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else : params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); : does this make any sense at all? first setting D3HotEnable to the dt value, then overriding it? -- To view, visit https://review.coreboot.org/c/coreboot/+/72800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Gerrit-Change-Number: 72800 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:50:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Sean Rhodes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72800 ) Change subject: soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT ...................................................................... Patch Set 8: (3 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/72800/comment/12e2a27f_b457c748 PS4, Line 997: NO_S0IX_SUPPORT as already said, there is a devicetree option. https://review.coreboot.org/c/coreboot/+/72800/comment/f94ce603_abf71435 PS4, Line 1004: Don't support D3Cold" : default n if NO_S0IX_SUPPORT "Don't support" but Kconfig name says "support". What?? https://review.coreboot.org/c/coreboot/+/72800/comment/e50fb206_bf7cb64d PS4, Line 997: config NO_S0IX_SUPPORT : bool "Don't support S0IX suspend" : default n : help : Select if the board only supports S3 and/or S4 and not S0IX : : config D3COLD_SUPPORT : bool "Don't support D3Cold" : default n if NO_S0IX_SUPPORT : default y : help : Select is any devices don't support D3Cold state : : this change is doing more than just "hooking up", while the previous change, does not add these Kconfigs, while claiming so. guys.... -- To view, visit https://review.coreboot.org/c/coreboot/+/72800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Gerrit-Change-Number: 72800 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:48:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/dell: Add Latitude E6220
by Evgeny Zinoviev (Code Review) 07 Apr '23

07 Apr '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74287 ) Change subject: mb/dell: Add Latitude E6220 ...................................................................... mb/dell: Add Latitude E6220 Just autoported. Not tested, thus doesn't work yet with 99% probability. Please don't comment obvious stuff until it's ready for review. :) Change-Id: Id03357d39036872b433505ce2930166fe82d0021 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/dell/e6220/Kconfig A src/mainboard/dell/e6220/Kconfig.name A src/mainboard/dell/e6220/Makefile.inc A src/mainboard/dell/e6220/acpi/ec.asl A src/mainboard/dell/e6220/acpi/platform.asl A src/mainboard/dell/e6220/acpi/superio.asl A src/mainboard/dell/e6220/acpi_tables.c A src/mainboard/dell/e6220/board_info.txt A src/mainboard/dell/e6220/devicetree.cb A src/mainboard/dell/e6220/dsdt.asl A src/mainboard/dell/e6220/early_init.c A src/mainboard/dell/e6220/gma-mainboard.ads A src/mainboard/dell/e6220/gpio.c A src/mainboard/dell/e6220/hda_verb.c A src/mainboard/dell/e6220/mainboard.c 15 files changed, 567 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74287/1 diff --git a/src/mainboard/dell/e6220/Kconfig b/src/mainboard/dell/e6220/Kconfig new file mode 100644 index 0000000..2fc8e28 --- /dev/null +++ b/src/mainboard/dell/e6220/Kconfig @@ -0,0 +1,36 @@ +if BOARD_DELL_LATITUDE_E6220 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_10240 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "dell/latitude_e6220" + +config MAINBOARD_PART_NUMBER + string + default "Latitude E6220" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/e6220/Kconfig.name b/src/mainboard/dell/e6220/Kconfig.name new file mode 100644 index 0000000..678d173 --- /dev/null +++ b/src/mainboard/dell/e6220/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_LATITUDE_E6220 + bool "Latitude E6220" diff --git a/src/mainboard/dell/e6220/Makefile.inc b/src/mainboard/dell/e6220/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/e6220/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/e6220/acpi/ec.asl b/src/mainboard/dell/e6220/acpi/ec.asl new file mode 100644 index 0000000..0d429410 --- /dev/null +++ b/src/mainboard/dell/e6220/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 16) +/* FIXME: EC support */ +} diff --git a/src/mainboard/dell/e6220/acpi/platform.asl b/src/mainboard/dell/e6220/acpi/platform.asl new file mode 100644 index 0000000..2d24bbd --- /dev/null +++ b/src/mainboard/dell/e6220/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/e6220/acpi/superio.asl b/src/mainboard/dell/e6220/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/dell/e6220/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/e6220/acpi_tables.c b/src/mainboard/dell/e6220/acpi_tables.c new file mode 100644 index 0000000..e275965 --- /dev/null +++ b/src/mainboard/dell/e6220/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/e6220/board_info.txt b/src/mainboard/dell/e6220/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/dell/e6220/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/e6220/devicetree.cb b/src/mainboard/dell/e6220/devicetree.cb new file mode 100644 index 0000000..340c879 --- /dev/null +++ b/src/mainboard/dell/e6220/devicetree.cb @@ -0,0 +1,94 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2300" + register "gpu_panel_power_backlight_on_delay" = "2300" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "400" + register "gpu_panel_power_up_delay" = "400" + register "gpu_pch_backlight" = "0x13121312" + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x007c0901" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x001c0901" + register "gpi0_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3b" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device ref mei1 on # Management Engine Interface 1 + subsystemid 0x1028 0x04a9 + end + device ref mei2 off # Management Engine Interface 2 + end + device ref me_ide_r off # Management Engine IDE-R + end + device ref me_kt off # Management Engine KT + end + device ref gbe on # Intel Gigabit Ethernet + subsystemid 0x1028 0x04a9 + end + device ref ehci2 on # USB2 EHCI #2 + subsystemid 0x1028 0x04a9 + end + device ref hda on # High Definition Audio + subsystemid 0x1028 0x04a9 + end + device ref pcie_rp1 on # PCIe Port #1 + subsystemid 0x1028 0x04a9 + end + device ref pcie_rp2 on # PCIe Port #2 + subsystemid 0x1028 0x04a9 + end + device ref pcie_rp3 on # PCIe Port #3 + subsystemid 0x1028 0x04a9 + end + device ref pcie_rp4 off # PCIe Port #4 + end + device ref pcie_rp5 off # PCIe Port #5 + end + device ref pcie_rp6 on # PCIe Port #6 + subsystemid 0x1028 0x04a9 + end + device ref pcie_rp7 off # PCIe Port #7 + end + device ref pcie_rp8 off # PCIe Port #8 + end + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x1028 0x04a9 + end + device ref pci_bridge off # PCI bridge + end + device ref lpc on # LPC bridge + subsystemid 0x1028 0x04a9 + end + device ref sata1 on # SATA Controller 1 Unsupported PCI device 8086:282a + subsystemid 0x1028 0x04a9 + end + device ref smbus on # SMBus + subsystemid 0x1028 0x04a9 + end + device ref sata2 off # SATA Controller 2 + end + device ref thermal off # Thermal + end + end + device ref host_bridge on # Host bridge Host bridge + subsystemid 0x1028 0x04a9 + end + device ref peg10 off # PEG + end + device ref igd on # iGPU + subsystemid 0x1028 0x04a9 + end + end +end diff --git a/src/mainboard/dell/e6220/dsdt.asl b/src/mainboard/dell/e6220/dsdt.asl new file mode 100644 index 0000000..7d13c55 --- /dev/null +++ b/src/mainboard/dell/e6220/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/e6220/early_init.c b/src/mainboard/dell/e6220/early_init.c new file mode 100644 index 0000000..05e5382 --- /dev/null +++ b/src/mainboard/dell/e6220/early_init.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/e6220/gma-mainboard.ads b/src/mainboard/dell/e6220/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/dell/e6220/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/e6220/gpio.c b/src/mainboard/dell/e6220/gpio.c new file mode 100644 index 0000000..2306e4c --- /dev/null +++ b/src/mainboard/dell/e6220/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/e6220/hda_verb.c b/src/mainboard/dell/e6220/hda_verb.c new file mode 100644 index 0000000..2085b62 --- /dev/null +++ b/src/mainboard/dell/e6220/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x102804a9, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102804a9), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/e6220/mainboard.c b/src/mainboard/dell/e6220/mainboard.c new file mode 100644 index 0000000..1c023eb --- /dev/null +++ b/src/mainboard/dell/e6220/mainboard.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x33, 0x00, 0x04, 0x00, 0x00, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x64, 0x00, 0x00, 0x7c, 0x30, 0xe0, 0x15, 0xe7, 0x0b, 0x28, 0x47, 0x00, 0x00, 0x9f, 0x0b, + /* 20 */ 0xe0, 0x15, 0x5c, 0x2b, 0x03, 0x3f, 0x62, 0x0c, 0x03, 0x02, 0x00, 0x00, 0x00, 0xff, 0x00, 0xff, + /* 30 */ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/74287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03357d39036872b433505ce2930166fe82d0021 Gerrit-Change-Number: 74287 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS
by Nico Huber (Code Review) 07 Apr '23

07 Apr '23

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73449 ) Change subject: cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > > Is this a good idea? The SI prefix seems to be applied to mostly Intel boards. […] I think generally using the coreboot build-system as a general stitching/verfication tool for out-of-scope, proprietary components is not a good idea. In this particular case, I assume both the IFD and the correct CBFS_SIZE setting come from outside the coreboot repository. So it might be better to validate them there? Doesn't mean ifdtool couldn't be extended to validate whatever is necessary, e.g. in this case having an option to specify the region name to assume as matching IFD/BIOS would be one way. -- To view, visit https://review.coreboot.org/c/coreboot/+/73449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2 Gerrit-Change-Number: 73449 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:46:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS
by Maximilian Brune (Code Review) 07 Apr '23

07 Apr '23

Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73449 ) Change subject: cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Is this a good idea? The SI prefix seems to be applied to mostly Intel boards. The default is BIOS everywhere else. Why should the default FMAP name change? I changed the FMAP name because if I use the name "BIOS" for validation in the ifdtool, then it will break all FMAPs that actually use the name "SI_BIOS" (almost all mainboards in the tree use it). If I use SI_BIOS on the other hand it will break the default-x86.fmd. So there is currently no way to validate the BIOS region if we use the default-x86.fmd. The easiest alternative that comes to mind is adding a default-intel.fmd file, but that feels wrong considering that we would only create it because of the bios region name. Any ideas on how to resolve this? > I also don't understand this: how could the auto-generated region match what > ifdtool --validate expects? I guess it would only work with specific, manual > configurations. You are right. Most of the time the BIOS region will not match. Guess we either need to validate the BIOS region differently (e.g. checking that the BIOS FMAP region fits in the SI_BIOS IFD region) or do not validate it at all. I tested it in my setup, but unlucky enough I chose a very big CBFS_SIZE because I wanted to stuck a Linux kernel in it. That resulted in a matching BIOS region. And we have no defconfig in the tree that actually selects the VALIDATE_INTEL_DESCRIPTOR option therefore jenkins didn't complain either. -- To view, visit https://review.coreboot.org/c/coreboot/+/73449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2 Gerrit-Change-Number: 73449 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:29:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72799 ) Change subject: device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: erm, so now we have both Kconfig AND devicetree, which can even be inconsistent? o.O -- To view, visit https://review.coreboot.org/c/coreboot/+/72799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Gerrit-Change-Number: 72799 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block: Add LPC BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71954 ) Change subject: soc/intel/common/block: Add LPC BIOS decode lock ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > This also needs to be set in the corresponding DMI register. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Gerrit-Change-Number: 71954 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:23:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Simon Chou. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71953 ) Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > This also needs to be set in the corresponding DMI register. […] ouch, sorry for double-posting... browser fail o.O -- To view, visit https://review.coreboot.org/c/coreboot/+/71953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Gerrit-Change-Number: 71953 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:23:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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