coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71953 ) Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: This also needs to be set in the corresponding DMI register. Take a look at how this was done for LPCIOE/LPCIOD CB:49592 -- To view, visit https://review.coreboot.org/c/coreboot/+/71953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Gerrit-Change-Number: 71953 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:22:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block: Add LPC BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71954 ) Change subject: soc/intel/common/block: Add LPC BIOS decode lock ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: This also needs to be set in the corresponding DMI register. Take a look at how this was done for LPCIOE/LPCIOD CB:49592 -- To view, visit https://review.coreboot.org/c/coreboot/+/71954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Gerrit-Change-Number: 71954 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block: Add LPC BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71954 ) Change subject: soc/intel/common/block: Add LPC BIOS decode lock ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: This also needs to be set in the corresponding DMI register. Take a look at how this was done for LPCIOE/LPCIOD CB:49592 -- To view, visit https://review.coreboot.org/c/coreboot/+/71954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Gerrit-Change-Number: 71954 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:21:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
by Michael Niewöhner (Code Review) 07 Apr '23

07 Apr '23

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71953 ) Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: This also needs to be set in the corresponding DMI register. Take a look at how this was done for LPCIOE/LPCIOD CB:49592 -- To view, visit https://review.coreboot.org/c/coreboot/+/71953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Gerrit-Change-Number: 71953 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Ryback Hung <ryback.hung(a)quantatw.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash
by Nico Huber (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74260 ) Change subject: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: I have a feeling that the current mmap API is only prepared for permanently mapped flash. In what situations/places in the code do you intend to use the mmap API? -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 Apr 2023 16:14:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Build for chromeOS
by Karthik Ramasubramanian (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74097 ) Change subject: mb/google/myst: Build for chromeOS ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Gerrit-Change-Number: 74097 Gerrit-PatchSet: 17 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 15:44:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"
by Felix Singer (Code Review) 07 Apr '23

07 Apr '23

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74290 ) Change subject: Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Landed early to fix the issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/74290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Gerrit-Change-Number: 74290 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Apr 2023 15:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"
by Felix Singer (Code Review) 07 Apr '23

07 Apr '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74290 ) Change subject: Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS" ...................................................................... Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS" This reverts commit 89b4f69746ac215e4a7c5f204d1ea807b4ea08b5. SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all platforms are Intel platforms with an IFD, so revert this change. Also tooling often depends on names not changing so renaming things should not be done lightly. The default region should also be in sync with non-x86 and made systematic across the tree. Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M util/cbfstool/default-x86.fmd 1 file changed, 27 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, approved Matt DeVillier: Looks good to me, approved Felix Singer: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index 8991a81..41be782 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -8,7 +8,7 @@ # +-------------+ <-- 4GB / end of flash FLASH@##ROM_BASE## ##ROM_SIZE## { - SI_BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## -- To view, visit https://review.coreboot.org/c/coreboot/+/74290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Gerrit-Change-Number: 74290 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash
by Bao Zheng (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74260 to look at the new patch set (#5). Change subject: soc/amd/spi: Add xlate_windows to mmap 32M/64M flash ...................................................................... soc/amd/spi: Add xlate_windows to mmap 32M/64M flash For the flash size bigger than 16M, AMD SOC maps only one 16M page at a time and use SPI ROM page register to switch pages. We use "translated region device" to let CBFS and flashmap access the physical SPI device not being aware the existence of the switcher. We need to switch back to page 0 in munmap because the FSP relies on this fact. This is one of series of patches to support 32/64M flash. The most important one. BUG=b:255374782 Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/spi/Kconfig M src/soc/amd/common/block/spi/Makefile.inc A src/soc/amd/common/block/spi/spi_map_big.c 3 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74260/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Michał Żygowski (Code Review) 07 Apr '23

07 Apr '23

Attention is currently required from: Maciej Pijanowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 17: (21 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73934/comment/9beb322b_7451f6ea PS4, Line 11: Document Number: 618876 > Corrected, in current commit (Patchset #9) Ack File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/d85f26e4_60c92e0f PS17, Line 15: "ESPI_RESET,_N", "ESPI_RESET_N" https://review.coreboot.org/c/coreboot/+/73934/comment/2efead11_eb905683 PS17, Line 18: "SMB_ALERT_,N", "SMB_ALERT_N" https://review.coreboot.org/c/coreboot/+/73934/comment/83ef1e42_636acd07 PS17, Line 148: "GPP_L_BKLTEN", "GPP_L_BKLTEN", : "GPP_L_BKLTCTL", "GPP_L_BKLTCTL", : "GPP_LVDDEN", "GPP_LVDDEN", : "GPP_SYS_PWROK", "GPP_SYS_PWROK", : "GPP_SYS_RESETB", "GPP_SYS_RESETB", : "GPP_MLK_RSTB", "GPP_MLK_RSTB", These pins should not have GPP_ prefix https://review.coreboot.org/c/coreboot/+/73934/comment/b2fbd389_857656fd PS17, Line 157: GPP_HVCMOS Just HVCMOS https://review.coreboot.org/c/coreboot/+/73934/comment/9b0eb9eb_84eb3c1e PS17, Line 503: const char *const jasperlake_pch_group_vgpio_padding_names [] ={ Just jasperlake_pch_group_vgpio_names and jasperlake_pch_group_vgpio Here and everywhere for this group https://review.coreboot.org/c/coreboot/+/73934/comment/85ccf103_c21c61d9 PS17, Line 554: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", : "GPD_SLP_SUSB", "GPD_SLP_SUSB", : "GPD_WAKEB", "GPD_WAKEB", : "GPD_DRAM_RESETB", "GPD_DRAM_RESETB", These should not have GPD_ prefix File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/5ae00834_1dd0a4c2 PS12, Line 539: // Deep Sleep Well group > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/7bbd8c7c_bd7f9389 PS12, Line 553: "GPD_INPUT3VSEL", "GPD_INPUT3VSEL", > Done Ack https://review.coreboot.org/c/coreboot/+/73934/comment/13179688_8439233f PS12, Line 584: > Done Ack File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/879a1884_81233b37 PS4, Line 141: "L_BLKTEN", : "L_BLKTCTL", : "LVDDEN", : "SYS_PWROK", : "SYS_RESETB", : "MLK_RSTB", > Corrected, in Patchset #8 Ack https://review.coreboot.org/c/coreboot/+/73934/comment/9e852f0e_46657d1a PS4, Line 191: "JTAG_TD0", : "JTAGX", : "PRDYB", : "PREQB", : "CPU_TRSTB", : "JTAG_TDI", : "JTAG_TMS", : "JTAG_TCK", : "ITP_PMODE" > Corrected, in patchset #8 Ack https://review.coreboot.org/c/coreboot/+/73934/comment/5dd092da_c53db664 PS4, Line 266: "GPP_H15", "AVS_I2S1_SCLK", "n/a", "n/a", > Ack, corrected in my working copy, will be visible after pushing. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/266442d8_6cf6ba51 PS4, Line 281: "GSPI2_CLK_LOOPBK", : "SPI1_CLK_LOOPBK", > Corrected, in patchset #9. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/db40cd9a_309c53ce PS4, Line 312: "GSPI0_CLK_LOOPBK", : "GSPI1_CLK_LOOPBK", > Corrected, in patchset #9. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/c383184e_45c577d5 PS4, Line 336: .pad_count = ARRAY_SIZE(jasperlake_pch_group_r_names) / 6, : .func_count = 6, > Corrected. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/f9666043_ecf35e05 PS4, Line 354: .pad_count = ARRAY_SIZE(jasperlake_pch_group_s_names) / 2, : .func_count = 2, > Corrected. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/952fa78e_c8707db9 PS4, Line 361: "HDACPU_SDI", : "HDACPU_SDO", : "HDACPU_SCLK", : "PM_SYNC", : "PECI", : "CPUPWRGD", : "THRMTRIPB", : "PLTRST_CPUB", : "PM_DOWN", : "TRIGGER_IN", : "TRIGGER_OUT", : "UFS_RESETB", : "CLKOUT_CPURTC", : "VCCST_PWRGD", : "C10_WAKE", > Corrected. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/d1453600_6dd7cbf3 PS4, Line 386: "VGPIO_PCIE0", : "VGPIO_PCIE1", : "VGPIO_PCIE2", : "VGPIO_PCIE3", : "VGPIO_PCIE4", : "VGPIO_PCIE5", : "VGPIO_PCIE6", : "VGPIO_PCIE7", : "VGPIO_PCIE8", : "VGPIO_PCIE9", : "VGPIO_PCIE10", : "VGPIO_PCIE11", : "VGPIO_PCIE12", : "VGPIO_PCIE13", : "VGPIO_PCIE14", : "VGPIO_PCIE15", : "VGPIO_PCIE16", : "VGPIO_PCIE17", : "VGPIO_PCIE18", : "VGPIO_PCIE19", : "VGPIO_PCIE20", : "VGPIO_PCIE21", : "VGPIO_PCIE22", : "VGPIO_PCIE23", : "VGPIO_PCIE24", : "VGPIO_PCIE25", : "VGPIO_PCIE26", : "VGPIO_PCIE27", : "VGPIO_PCIE28", : "VGPIO_PCIE29", : "VGPIO_PCIE30", : "VGPIO_PCIE31", : "VGPIO_PCIE32", : "VGPIO_PCIE33", : "VGPIO_PCIE34", : "VGPIO_PCIE35", : "VGPIO_PCIE36", : "VGPIO_PCIE37", : "VGPIO_PCIE38", : "VGPIO_PCIE39", : "VGPIO_PCIE40", : "VGPIO_PCIE41", : "VGPIO_PCIE42", : "VGPIO_PCIE43", : "VGPIO_PCIE44", : "VGPIO_PCIE45", : "VGPIO_PCIE46", : "VGPIO_PCIE47", : "VGPIO_PCIE48", : "VGPIO_PCIE49", : "VGPIO_PCIE50", : "VGPIO_PCIE51", : "VGPIO_PCIE52", : "VGPIO_PCIE53", : "VGPIO_PCIE54", : "VGPIO_PCIE55", : "VGPIO_PCIE56", : "VGPIO_PCIE57", : "VGPIO_PCIE58", : "VGPIO_PCIE59", : "VGPIO_PCIE60", : "VGPIO_PCIE61", : "VGPIO_PCIE62", : "VGPIO_PCIE63", : "VGPIO_PCIE64", : "VGPIO_PCIE65", : "VGPIO_PCIE66", : "VGPIO_PCIE67", : "VGPIO_PCIE68", : "VGPIO_PCIE69", : "VGPIO_PCIE70", : "VGPIO_PCIE71", : "VGPIO_PCIE72", : "VGPIO_PCIE73", : "VGPIO_PCIE74", : "VGPIO_PCIE75", : "VGPIO_PCIE76", : "VGPIO_PCIE77", : "VGPIO_PCIE78", : "VGPIO_PCIE79", > Corrected. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/dddfa0f6_65474fbe PS4, Line 475: "VGPIO_USB0", : "VGPIO_USB1", : "VGPIO_USB2", : "VGPIO_USB3", : "VGPIO_USB4", : "VGPIO_USB5", : "VGPIO_USB6", : "VGPIO_USB7", : "VGPIO_USB8", : "VGPIO_USB9", : "VGPIO_USB10", : "VGPIO_USB11", > Corrected. Ack https://review.coreboot.org/c/coreboot/+/73934/comment/4c4231a6_9760e8bc PS4, Line 511: const struct gpio_group jasperlake_pch_group_dsw = { : .display = "------- GPIO Group GPP_S -------", : .pad_count = ARRAY_SIZE(jasperlake_pch_group_dsw_names) / 2, : .func_count = 2, : .pad_names = jasperlake_pch_group_s_names, : }; : : const struct gpio_group jasperlake_pch_group_vgpio_pcie = { : .display = "------- GPIO Group GPP_S -------", : .pad_count = ARRAY_SIZE(jasperlake_pch_group_dsw_names) / 2, : .func_count = 2, : .pad_names = jasperlake_pch_group_s_names, : }; > Two GPP_S groups, both using jasperlake_pch_group_dsw_names and jasperlake_pch_group_s_names and nam […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 17 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Fri, 07 Apr 2023 15:10:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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coreboot-gerrit April 2023