coreboot-gerrit April 2023

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[S] Change in coreboot[master]: Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SU...
by Michael Niewöhner (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Felix Singer, Sean Rhodes, Angel Pons, Martin Roth, Lean Sheng Tan. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73903 ) Change subject: Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT" ...................................................................... Patch Set 4: (2 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/73903/comment/8746bb09_e50295b6 PS4, Line 997: NO_S0IX_SUPPORT for reference: https://review.coreboot.org/c/coreboot/+/72800/4..8/src/device/Kconfig#b997 https://review.coreboot.org/c/coreboot/+/72799/comments/2c2413f5_79bb9d29 https://review.coreboot.org/c/coreboot/+/73903/comment/2ced25ef_764e8488 PS4, Line 1003: config D3COLD_SUPPORT : bool "Don't support D3Cold" for reference: https://review.coreboot.org/c/coreboot/+/72800/4..8/src/device/Kconfig#b1005 -- To view, visit https://review.coreboot.org/c/coreboot/+/73903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56ce8f59f8548fc58bc2b3b07c1314e2eed7061c Gerrit-Change-Number: 73903 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 08 Apr 2023 07:31:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/sandybridge/romstage: Use POST_CONSOLE_READY macro
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/64170 ) Change subject: nb/intel/sandybridge/romstage: Use POST_CONSOLE_READY macro ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/64170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01466a78a024ea1d170215a8eea3691780fb5fb Gerrit-Change-Number: 64170 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: cpu/x86/mtrr/mtrr: Use POST_FSP_SILICON_INIT macro
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/64140 ) Change subject: cpu/x86/mtrr/mtrr: Use POST_FSP_SILICON_INIT macro ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/64140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If860b26ab4bac523e53fc5676798aa7bfbb45468 Gerrit-Change-Number: 64140 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: crossgcc: Upgrade IASL from 20221020 to 20230331
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Felix Singer, Martin L Roth. Hello Felix Singer, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74272 to look at the new patch set (#3). Change subject: crossgcc: Upgrade IASL from 20221020 to 20230331 ...................................................................... crossgcc: Upgrade IASL from 20221020 to 20230331 Changes: https://acpica.org/node/202 Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20230331_iasl.patch D util/crossgcc/sum/R10_20_22.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20230331.tar.gz.cksum 4 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74272/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90 Gerrit-Change-Number: 74272 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74289 ) Change subject: crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3 ...................................................................... crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3 Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.26.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum 3 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/74289/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4f13606..71818dd 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -42,7 +42,7 @@ IASL_VERSION="R10_20_22" # CLANG version number CLANG_VERSION=15.0.7 -CMAKE_VERSION=3.26.2 +CMAKE_VERSION=3.26.3 NASM_VERSION=2.15.05 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.26.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.26.2.tar.gz.cksum deleted file mode 100644 index 98d4070..0000000 --- a/util/crossgcc/sum/cmake-3.26.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -b2629a8077e92213605b4f7e7cfc6d94416b5396 tarballs/cmake-3.26.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum new file mode 100644 index 0000000..cac6425 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum @@ -0,0 +1 @@ +03881b9004a56b5b324503f48ded62afb55a5f52 tarballs/cmake-3.26.3.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/74289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126 Gerrit-Change-Number: 74289 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Paul Menzel, Angel Pons, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Jason Glenesk, Martin L Roth, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73792 to look at the new patch set (#11). Change subject: crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1 ...................................................................... crossgcc: Upgrade LLVM version 15.0.7 to 16.0.1 Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/clang-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/cmake-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-16.0.1.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum A util/crossgcc/sum/llvm-16.0.1.src.tar.xz.cksum 11 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73792/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/73792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Gerrit-Change-Number: 73792 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73810 ) Change subject: ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int' ...................................................................... ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/lenovo/pmh7/chip.h M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M util/autoport/ec_lenovo.go 21 files changed, 63 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 1302139..896578f 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -3,9 +3,11 @@ #ifndef EC_LENOVO_PMH7_CHIP_H #define EC_LENOVO_PMH7_CHIP_H +#include <stdbool.h> + struct ec_lenovo_pmh7_config { - int backlight_enable:1; - int dock_event_enable:1; + bool backlight_enable; + bool dock_event_enable; }; #endif /* EC_LENOVO_PMH7_CHIP_H */ diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index fb05027..f8467c7 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -55,8 +55,8 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1f.0 on # LPC bridge chip ec/lenovo/pmh7 - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" device pnp ff.1 on end # dummy end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index 292a30d..0d705fb 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -54,8 +54,8 @@ device pci 1d.0 on end # USB2 EHCI #1 device pci 1f.0 on # LPC bridge chip ec/lenovo/pmh7 - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" device pnp ff.1 on end # dummy end chip ec/lenovo/h8 # FIXME: has_power_management_beeps, has_uwb diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index a012741..dd431df 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -54,8 +54,8 @@ device ref pci_bridge off end # PCI bridge device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" device pnp ff.1 on end # dummy end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 1df350a..259c3e1 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -120,8 +120,8 @@ chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 200cabb..8d4ab5f 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -99,8 +99,8 @@ end chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip ec/lenovo/h8 device pnp ff.2 on # dummy diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 33070eb..953044a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -77,8 +77,8 @@ device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index b5576b2..fc3b12c 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -75,8 +75,8 @@ device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 7e54383..35c23b8 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -64,8 +64,8 @@ device ref pci_bridge off end # PCI bridge device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" device pnp ff.1 on end # dummy end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 175a5c8..23a41d6 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -77,8 +77,8 @@ device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 7ef12ba2..3cb18b4 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -73,8 +73,8 @@ device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index d47acda..becc357 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -78,8 +78,8 @@ device ref lpc on # PCI-LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f72b2e9..25782e97 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -109,8 +109,8 @@ subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip ec/lenovo/h8 device pnp ff.2 on # dummy diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 704a410..a423246 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -77,8 +77,8 @@ device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 6ddd090..7871cfd 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -110,7 +110,7 @@ chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" + register "backlight_enable" = "true" end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb index 51beecc..cd69e2e 100644 --- a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb +++ b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb @@ -17,7 +17,7 @@ device pci 1f.0 on # LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "dock_event_enable" = "0x01" + register "dock_event_enable" = "true" end chip superio/nsc/pc87382 device pnp 164e.3 on # Digitizer diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index fc7c470..6c27f53 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -106,8 +106,8 @@ chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip ec/lenovo/h8 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index eb79baa..7a99599 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -78,8 +78,8 @@ device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 490f837..fdd5059 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -80,8 +80,8 @@ device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip drivers/pc80/tpm diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index f63acf7..0e1e5fc 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -97,8 +97,8 @@ subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" + register "backlight_enable" = "true" + register "dock_event_enable" = "true" end chip ec/lenovo/h8 device pnp ff.2 on # dummy diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 9a02ac3..a34960f 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -155,8 +155,8 @@ pmh := DevTreeNode{ Chip: "ec/lenovo/pmh7", Registers: map[string]string{ - "backlight_enable": "0x01", - "dock_event_enable": "0x01", + "backlight_enable": "true", + "dock_event_enable": "true", }, Children: []DevTreeNode{ DevTreeNode{ -- To view, visit https://review.coreboot.org/c/coreboot/+/73810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Gerrit-Change-Number: 73810 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73796 ) Change subject: sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' ...................................................................... sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h 11 files changed, 39 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index dd701da..fd86e93 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -52,10 +52,10 @@ register "ide_enable_primary" = "true" register "ide_enable_secondary" = "true" - register "c4onc3_enable" = "1" + register "c4onc3_enable" = "true" register "c3_latency" = "0x23" - register "p_cnt_throttling_supported" = "1" + register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index f6d5f76..c464222 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -33,7 +33,7 @@ register "ide_enable_primary" = "true" register "ide_enable_secondary" = "false" - register "p_cnt_throttling_supported" = "0" + register "p_cnt_throttling_supported" = "false" # SuperIO Power Management Events register "gen1_dec" = "0x00040291" diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index b12335e..86bae67 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -43,7 +43,7 @@ register "c3_latency" = "85" register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" + register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x001c02e1" register "gen2_dec" = "0x00fc0601" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 576be34..0aa91b2 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -58,7 +58,7 @@ register "ide_enable_secondary" = "false" register "c3_latency" = "85" - register "p_cnt_throttling_supported" = "0" + register "p_cnt_throttling_supported" = "false" register "gen1_dec" = "0x000c0801" # ??? register "gen2_dec" = "0x00040291" # Environment Controller diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 611bd96..93f3640 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -33,7 +33,7 @@ register "ide_enable_secondary" = "false" register "c3_latency" = "85" - register "p_cnt_throttling_supported" = "0" + register "p_cnt_throttling_supported" = "false" register "gen1_dec" = "0x00fc0291" register "gen4_dec" = "0x00000301" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 4007e7e..70a3819 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -34,7 +34,7 @@ register "ide_enable_primary" = "true" register "ide_enable_secondary" = "false" register "c3_latency" = "85" - register "p_cnt_throttling_supported" = "0" + register "p_cnt_throttling_supported" = "false" register "gen1_dec" = "0x0007c0681" # SuperIO Power Management diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index cd67480..5e392e6 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -33,7 +33,7 @@ register "ide_enable_primary" = "true" register "ide_enable_secondary" = "true" register "c3_latency" = "85" - register "p_cnt_throttling_supported" = "0" + register "p_cnt_throttling_supported" = "false" # ICH-7 generic decode IO ports range for LPC register "gen1_dec" = "0x00fc0a01" # HWM diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 913b732..f72b2e9 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -58,10 +58,10 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" - register "c4onc3_enable" = "1" + register "c4onc3_enable" = "true" register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" + register "docking_supported" = "true" + register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index d7c86a5..f63acf7 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -51,11 +51,11 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" - register "c4onc3_enable" = "1" + register "c4onc3_enable" = "true" register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" + register "docking_supported" = "true" + register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index a3b00c1..52c96de 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -38,7 +38,7 @@ register "c3_latency" = "0x23" register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" + register "p_cnt_throttling_supported" = "true" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" register "ide_enable_primary" = "true" diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index ba8dd6f..04b82d3 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -63,9 +63,9 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ bool pcie_port_coalesce; - int c4onc3_enable:1; - int docking_supported:1; - int p_cnt_throttling_supported:1; + bool c4onc3_enable; + bool docking_supported; + bool p_cnt_throttling_supported; int c3_latency; /* Additional LPC IO decode ranges */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Gerrit-Change-Number: 73796 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: sb/intel/i82371eb/chip.h: Use 'bool' instead of 'int'
by Elyes Haouas (Code Review) 08 Apr '23

08 Apr '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73794 ) Change subject: sb/intel/i82371eb/chip.h: Use 'bool' instead of 'int' ...................................................................... sb/intel/i82371eb/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: CC romstage/mainboard/emulation/qemu-i440fx/static.o build/mainboard/emulation/qemu-i440fx/static.c:31:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide0_enable = 1, ^ build/mainboard/emulation/qemu-i440fx/static.c:32:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide1_enable = 1, ^ Change-Id: I36cc19bc2908119fe940941e108ee217a7b26f50 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73794 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/asus/p2b/devicetree.cb M src/mainboard/emulation/qemu-i440fx/devicetree.cb M src/southbridge/intel/i82371eb/chip.h 3 files changed, 41 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index a650552..42bdade 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -42,14 +42,14 @@ device pci 4.1 on end # IDE device pci 4.2 on end # USB device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" + register "ide0_enable" = "true" + register "ide1_enable" = "true" + register "ide_legacy_enable" = "true" # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" + register "ide0_drive0_udma33_enable" = "true" + register "ide0_drive1_udma33_enable" = "true" + register "ide1_drive0_udma33_enable" = "true" + register "ide1_drive1_udma33_enable" = "true" register "thrm_polarity" = "1" register "lid_polarity" = "1" end diff --git a/src/mainboard/emulation/qemu-i440fx/devicetree.cb b/src/mainboard/emulation/qemu-i440fx/devicetree.cb index 385fa24..cecba1c 100644 --- a/src/mainboard/emulation/qemu-i440fx/devicetree.cb +++ b/src/mainboard/emulation/qemu-i440fx/devicetree.cb @@ -6,8 +6,8 @@ device pci 01.0 on end # ISA bridge device pci 01.1 on end # IDE device pci 01.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "true" + register "ide1_enable" = "true" register "gpo" = "0x7fffbbff" end end diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h index 264f74f..5652cd2 100644 --- a/src/southbridge/intel/i82371eb/chip.h +++ b/src/southbridge/intel/i82371eb/chip.h @@ -4,17 +4,18 @@ #define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H #include <device/device.h> +#include <types.h> struct southbridge_intel_i82371eb_config { - int ide0_enable:1; - int ide0_drive0_udma33_enable:1; - int ide0_drive1_udma33_enable:1; - int ide1_enable:1; - int ide1_drive0_udma33_enable:1; - int ide1_drive1_udma33_enable:1; - int ide_legacy_enable:1; - int usb_enable:1; - int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */ + bool ide0_enable; + bool ide0_drive0_udma33_enable; + bool ide0_drive1_udma33_enable; + bool ide1_enable; + bool ide1_drive0_udma33_enable; + bool ide1_drive1_udma33_enable; + bool ide_legacy_enable; + bool usb_enable; + bool gpo22_enable; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */ int gpo22:1; int gpo23:1; /* acpi */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36cc19bc2908119fe940941e108ee217a7b26f50 Gerrit-Change-Number: 73794 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/apple: Add MacBook Air 5,2 (A1466)
by Evgeny Zinoviev (Code Review) 08 Apr '23

08 Apr '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32604 Change subject: mb/apple: Add MacBook Air 5,2 (A1466) ...................................................................... mb/apple: Add MacBook Air 5,2 (A1466) This is WIP. Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/apple/macbookair5_2/Kconfig A src/mainboard/apple/macbookair5_2/Kconfig.name A src/mainboard/apple/macbookair5_2/Makefile.inc A src/mainboard/apple/macbookair5_2/acpi/ec.asl A src/mainboard/apple/macbookair5_2/acpi/platform.asl A src/mainboard/apple/macbookair5_2/acpi/superio.asl A src/mainboard/apple/macbookair5_2/acpi_tables.c A src/mainboard/apple/macbookair5_2/board_info.txt A src/mainboard/apple/macbookair5_2/devicetree.cb A src/mainboard/apple/macbookair5_2/dsdt.asl A src/mainboard/apple/macbookair5_2/gma-mainboard.ads A src/mainboard/apple/macbookair5_2/gnvs.c A src/mainboard/apple/macbookair5_2/gpio.c A src/mainboard/apple/macbookair5_2/hda_verb.c A src/mainboard/apple/macbookair5_2/mainboard.c A src/mainboard/apple/macbookair5_2/romstage.c A src/mainboard/apple/macbookair5_2/spd.bin 17 files changed, 843 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32604/1 diff --git a/src/mainboard/apple/macbookair5_2/Kconfig b/src/mainboard/apple/macbookair5_2/Kconfig new file mode 100644 index 0000000..853021f --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig @@ -0,0 +1,55 @@ +if BOARD_APPLE_MACBOOKAIR5_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookair5_2 + +config MAINBOARD_PART_NUMBER + string + default "MacBookAir5,2" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Apple Inc." + +endif diff --git a/src/mainboard/apple/macbookair5_2/Kconfig.name b/src/mainboard/apple/macbookair5_2/Kconfig.name new file mode 100644 index 0000000..d8a1fbf --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKAIR5_2 + bool "MacBookAir5,2" diff --git a/src/mainboard/apple/macbookair5_2/Makefile.inc b/src/mainboard/apple/macbookair5_2/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookair5_2/acpi/ec.asl b/src/mainboard/apple/macbookair5_2/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookair5_2/acpi/platform.asl b/src/mainboard/apple/macbookair5_2/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookair5_2/acpi/superio.asl b/src/mainboard/apple/macbookair5_2/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/superio.asl diff --git a/src/mainboard/apple/macbookair5_2/acpi_tables.c b/src/mainboard/apple/macbookair5_2/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookair5_2/board_info.txt b/src/mainboard/apple/macbookair5_2/board_info.txt new file mode 100644 index 0000000..cbd72ee --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: WSON-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookair5_2/devicetree.cb b/src/mainboard/apple/macbookair5_2/devicetree.cb new file mode 100644 index 0000000..efc5ddb --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/devicetree.cb @@ -0,0 +1,119 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "2" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000710" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "10" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "740" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x07100710" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x8086 0x7270 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00fe + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00fe + end + end +end diff --git a/src/mainboard/apple/macbookair5_2/dsdt.asl b/src/mainboard/apple/macbookair5_2/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookair5_2/gma-mainboard.ads b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookair5_2/gnvs.c b/src/mainboard/apple/macbookair5_2/gnvs.c new file mode 100644 index 0000000..def9e5f --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gnvs.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* the lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookair5_2/gpio.c b/src/mainboard/apple/macbookair5_2/gpio.c new file mode 100644 index 0000000..9f2cd14 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gpio.c @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookair5_2/hda_verb.c b/src/mainboard/apple/macbookair5_2/hda_verb.c new file mode 100644 index 0000000..6c8e555 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b5600, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b5600), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x0e2b4030), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookair5_2/mainboard.c b/src/mainboard/apple/macbookair5_2/mainboard.c new file mode 100644 index 0000000..d497c51 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/mainboard.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ +// { +// int i; +// const u8 dmp[256] = { +// /* 00 */ 0x40, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 10 */ 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 20 */ 0x00, 0x80, 0x16, 0x16, 0xe0, 0x40, 0x4f, 0x4e, 0x7a, 0x34, 0x35, 0x31, 0x38, 0x31, 0x32, 0x44, +// /* 30 */ 0x4b, 0x52, 0x4e, 0x41, 0x38, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, +// /* 40 */ 0x43, 0x44, 0x45, 0x00, 0x02, 0x14, 0x11, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 60 */ 0x03, 0x00, 0x00, 0x00, 0x0f, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// }; +// +// printk(BIOS_DEBUG, "Replaying EC dump ..."); +// for (i = 0; i < 256; i++) +// ec_write (i, dmp[i]); +// printk(BIOS_DEBUG, "done\n"); +// } + + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + +// /* FIXME: fix those values*/ +// install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, +// GMA_INT15_PANEL_FIT_DEFAULT, +// GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookair5_2/romstage.c b/src/mainboard/apple/macbookair5_2/romstage.c new file mode 100644 index 0000000..6594b15 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x00000401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); +} + +void mainboard_rcba_config(void) +{ + RCBA32(0x3414) = 0x00000020; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 512) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file + 256, 128); + } +} diff --git a/src/mainboard/apple/macbookair5_2/spd.bin b/src/mainboard/apple/macbookair5_2/spd.bin new file mode 100644 index 0000000..2e2a6b4 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/spd.bin Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/32604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447 Gerrit-Change-Number: 32604 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2023