coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
by John Su (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Jason Nien, Jason Glenesk, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74087 ) Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Reviewer Would you help to review this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/74087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b Gerrit-Change-Number: 74087 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 01:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Configure Acoustic noise mitigation
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73491 ) Change subject: mb/google/brya/var/marasov: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/marasov: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:271788117 TEST=build FW and system power on. Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73491 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck(a)google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Tracy Wu: Looks good to me, but someone else must approve Derek Huang: Looks good to me, approved Kyle Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index a138c27..79d5abb 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -24,6 +24,12 @@ end chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/73491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Gerrit-Change-Number: 73491 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Configure Acoustic noise mitigation
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Tarun Tuli, Frank Chu, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73491 ) Change subject: mb/google/brya/var/marasov: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please don't +1 to yourself. -- To view, visit https://review.coreboot.org/c/coreboot/+/73491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Gerrit-Change-Number: 73491 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 10 Apr 2023 01:17:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Declare CrOS GPIOs
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74096 ) ( 14 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Declare CrOS GPIOs ...................................................................... mb/google/myst: Declare CrOS GPIOs Declare CrOS GPIOs for Myst, add relevant defines needed by chromeOS for additional control GPIOs. BUG=b:270616013 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74096 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/google/myst/chromeos.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h 2 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c new file mode 100644 index 0000000..9f4a3cb --- /dev/null +++ b/src/mainboard/google/myst/chromeos.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h index b94afac..a6683fd 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h @@ -3,4 +3,9 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ +#include <gpio.h> + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_139 + #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9 Gerrit-Change-Number: 74096 Gerrit-PatchSet: 17 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: First pass GPIO configuration for Myst
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74095 ) ( 16 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: First pass GPIO configuration for Myst ...................................................................... mb/google/myst: First pass GPIO configuration for Myst Initial GPIO configuration for Myst. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74095 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/variants/baseboard/gpio.c 1 file changed, 178 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 4383d14..0add7a0 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -3,10 +3,169 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <gpio.h> /* GPIO configuration in ramstage*/ static const struct soc_amd_gpio base_gpio_table[] = { - /* TODO(b/270596581): Fill gpio configuration */ + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* Unused */ + PAD_NC(GPIO_3), + /* EN_PWR_FP */ + PAD_GPO(GPIO_4, LOW), + /* EN_PP3300_TCHPAD */ + PAD_GPO(GPIO_5, HIGH), + /* EN_PP3300_WWAN_X */ + PAD_GPO(GPIO_6, LOW), + /* SOC_PEN_DETECT_ODL */ + PAD_WAKE(GPIO_7, PULL_NONE, EDGE_LOW, S0i3), + /* SOC_TCHPAD_INT_ODL */ + PAD_SCI(GPIO_8, PULL_NONE, LEVEL_LOW), + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_9, HIGH), + /* WWAN_RST */ + PAD_GPO(GPIO_11, LOW), + /* Unused */ + PAD_NC(GPIO_12), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* EC_SOC_WAKE_R_ODL */ + PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), + /* FP_SOC_INT_L */ + PAD_SCI(GPIO_18, PULL_NONE, LEVEL_LOW), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* Unused */ + PAD_NC(GPIO_21), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_NONE), + /* Unused */ + PAD_NC(GPIO_24), + /* GPIO_25-26: Not available */ + /* SOC_PCIE_RST1_R_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* GPIO_28: Not available */ + /* SD_AUX_RST */ + PAD_GPO(GPIO_29, LOW), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* SSD_AUX_RST */ + PAD_GPO(GPIO_31, LOW), + /* LPC_RST_L */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), + /* GPIO_33 - GPIO_37: Not available */ + /* WLAN_AUX_RST_L */ + PAD_GPO(GPIO_38, HIGH), + /* WWAN_AUX_RST_L */ + PAD_GPO(GPIO_39, HIGH), + /* SOC_FP_RST_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41 - GPIO_66: Not available */ + /* GPIO_67 (Unused) */ + PAD_NC(GPIO_67), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* SOC_CLK_FPMCU_R TODO(276939271): Selectively init */ + PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), + /* EN_TCHSCR_REPORT */ + PAD_GPO(GPIO_74, LOW), + /* SOC_CLK_FPMCU_R_L TODO(276939271): Selectively init */ + PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* Unused */ + PAD_NC(GPIO_76), + /* ESPI_SOC_CLK_EC_R */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_78, PULL_NONE), + /* RAM_ID_1 */ + PAD_GPI(GPIO_79, PULL_NONE), + /* ESPI_SOC_D1_EC_R */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_SOC_D0_EC_R */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), + /* HP_INT_ODL */ + PAD_GPI(GPIO_89, PULL_NONE), + /* EC_SOC_INT_ODL */ + PAD_GPI(GPIO_90, PULL_NONE), + /* TCHSCR_INT_ODL */ + PAD_GPI(GPIO_91, PULL_NONE), + /* CLK_REQ0_L / WLAN */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* SPI_SOC_DO_FPMCU_DI_R TODO(276939271): Selectively init */ + PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), + /* SPI_SOC_DI_FPMCU_DO_R TODO(276939271): Selectively init */ + PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_106, PULL_NONE), + /* RAM_ID_3 */ + PAD_GPI(GPIO_107, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L / SD */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L / WWAN */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* Unused */ + PAD_NC(GPIO_130), + /* CLK_REQ3_L / SSD */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), + /* SOC_FP_BOOT0 */ + PAD_GPO(GPIO_132, LOW), + /* EN_PP3300_CAM */ + PAD_GPO(GPIO_135, HIGH), + /* Unused */ + PAD_NC(GPIO_136), + /* Unused */ + PAD_NC(GPIO_137), + /* Unused */ + PAD_NC(GPIO_138), + /* SOC_BIOS_WP_OD */ + PAD_GPI(GPIO_139, PULL_NONE), + /* UART1_TXD / FPMCU TODO(276939271): Selectively init */ + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + /* UART0_RXD / DBG */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART1_RXD / FPMCU TODO(276939271): Selectively init */ + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + /* UART0_TXD / DBG */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_144, HIGH), + /* I2C0_SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0_SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1_SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1_SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* EN_SPKR */ + PAD_GPO(GPIO_153, LOW), + /* BT_DISABLE */ + PAD_GPO(GPIO_154, LOW), + /* HDMI_RST */ + PAD_GPO(GPIO_155, HIGH), + /* WLAN_DISABLE */ + PAD_GPO(GPIO_156, LOW), + /* TCHSCR_RST_L */ + PAD_GPO(GPIO_157, HIGH), }; /* GPIO configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Gerrit-Change-Number: 74095 Gerrit-PatchSet: 18 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Add stubs to configure GPIOs
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74094 ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Add stubs to configure GPIOs ...................................................................... mb/google/myst: Add stubs to configure GPIOs Add configuration stubs for GPIOs to be implemented later. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74094 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/google/myst/bootblock.c M src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/gpio.c A src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 6 files changed, 99 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c index 90789c6..0877807 100644 --- a/src/mainboard/google/myst/bootblock.c +++ b/src/mainboard/google/myst/bootblock.c @@ -7,3 +7,12 @@ { /* TODO(b/275959717): Perform mainboard initialization */ } + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + variant_bootblock_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index 09118d4..bba9fc2 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -14,9 +14,21 @@ return fch_irq_map; } +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + baseboard_gpio_table(&base_gpios, &base_num_gpios); + variant_override_gpio_table(&override_gpios, &override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, + override_gpios, override_num_gpios); +} + static void mainboard_init(void *chip_info) { - /* TODO(b/270596581): Perform mainboard initialization */ + mainboard_configure_gpios(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c new file mode 100644 index 0000000..4383d14 --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* GPIO configuration in ramstage*/ +static const struct soc_amd_gpio base_gpio_table[] = { + /* TODO(b/270596581): Fill gpio configuration */ +}; + +/* GPIO configuration in bootblock */ +static const struct soc_amd_gpio bootblock_gpio_table[] = { + /* TODO(b/275965982): Fill bootblock gpio configuration */ +}; + +void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(base_gpio_table); + *gpio = base_gpio_table; +} + +__weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(bootblock_gpio_table); + *gpio = bootblock_gpio_table; +} + +__weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = 0; + *gpio = NULL; +} diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b94afac --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 927af2f..3f69548 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -3,4 +3,19 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ +#include <gpio.h> + + +/* This function provides base GPIO configuration table. */ +void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +/* This function provides GPIO init in bootblock. */ +void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by baseboard_gpio_table(). + */ +void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + #endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875 Gerrit-Change-Number: 74094 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... mb/google/myst: Add new mainboard Myst is a new Google mainboard with an AMD Phoenix SOC. BUG=b:270596106 TEST=util/abuild/abuild -t GOOGLE_MYST --clean Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- A src/mainboard/google/myst/Kconfig A src/mainboard/google/myst/Kconfig.name A src/mainboard/google/myst/Makefile.inc A src/mainboard/google/myst/board_info.txt A src/mainboard/google/myst/bootblock.c A src/mainboard/google/myst/chromeos.fmd A src/mainboard/google/myst/dsdt.asl A src/mainboard/google/myst/mainboard.c A src/mainboard/google/myst/port_descriptors.c A src/mainboard/google/myst/variants/baseboard/devicetree.cb A src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 11 files changed, 186 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig new file mode 100644 index 0000000..d8be3b8 --- /dev/null +++ b/src/mainboard/google/myst/Kconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_MYST + def_bool n + +if BOARD_GOOGLE_BASEBOARD_MYST + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_AMD_PHOENIX + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + +config MAINBOARD_DIR + default "google/myst" + +config MAINBOARD_FAMILY + string + default "Google_Myst" + +config MAINBOARD_PART_NUMBER + default "Myst" if BOARD_GOOGLE_MYST + +endif # BOARD_GOOGLE_BASEBOARD_MYST diff --git a/src/mainboard/google/myst/Kconfig.name b/src/mainboard/google/myst/Kconfig.name new file mode 100644 index 0000000..ab0e71c --- /dev/null +++ b/src/mainboard/google/myst/Kconfig.name @@ -0,0 +1,5 @@ +comment "Myst" + +config BOARD_GOOGLE_MYST + bool "-> Myst" + select BOARD_GOOGLE_BASEBOARD_MYST diff --git a/src/mainboard/google/myst/Makefile.inc b/src/mainboard/google/myst/Makefile.inc new file mode 100644 index 0000000..0315ba9 --- /dev/null +++ b/src/mainboard/google/myst/Makefile.inc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += port_descriptors.c + +ramstage-y += mainboard.c +ramstage-y += port_descriptors.c + +subdirs-y += variants/baseboard + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/myst/board_info.txt b/src/mainboard/google/myst/board_info.txt new file mode 100644 index 0000000..2969e6e --- /dev/null +++ b/src/mainboard/google/myst/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Myst +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c new file mode 100644 index 0000000..90789c6 --- /dev/null +++ b/src/mainboard/google/myst/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <baseboard/variants.h> + +void bootblock_mainboard_early_init(void) +{ + /* TODO(b/275959717): Perform mainboard initialization */ +} diff --git a/src/mainboard/google/myst/chromeos.fmd b/src/mainboard/google/myst/chromeos.fmd new file mode 100644 index 0000000..56a163d --- /dev/null +++ b/src/mainboard/google/myst/chromeos.fmd @@ -0,0 +1,39 @@ +# TODO(b/276944900): Update for 32 MB support, evaluate WP_RO size +FLASH@0xFF000000 16M { + SI_BIOS { + WP_RO 8M { + RO_GSCVD 8K + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + COREBOOT(CBFS) + GBB 12K + } + } + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + SIGNED_AMDFW_A 1536K + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + SIGNED_AMDFW_B 1536K + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 64K + RW_LEGACY(CBFS) + RW_VBIOS_CACHE 64K + RW_MRC_CACHE(PRESERVE) 256K + RECOVERY_MRC_CACHE(PRESERVE) 256K + } +} diff --git a/src/mainboard/google/myst/dsdt.asl b/src/mainboard/google/myst/dsdt.asl new file mode 100644 index 0000000..80a9c1f --- /dev/null +++ b/src/mainboard/google/myst/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include <acpi/dsdt_top.asl> + #include <soc.asl> +} diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c new file mode 100644 index 0000000..09118d4 --- /dev/null +++ b/src/mainboard/google/myst/mainboard.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/amd_pci_util.h> +#include <baseboard/variants.h> +#include <device/device.h> + +static const struct fch_irq_routing fch_irq_map[] = { + { 0, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void mainboard_init(void *chip_info) +{ + /* TODO(b/270596581): Perform mainboard initialization */ +} + +static void mainboard_enable(struct device *dev) +{ + /* TODO(b/270618107): Enable mainboard */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c new file mode 100644 index 0000000..9d3b15b --- /dev/null +++ b/src/mainboard/google/myst/port_descriptors.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/platform_descriptors.h> +#include <types.h> + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + /* TODO(b/276744321): Initialize DXIO and DDI descriptors */ +} diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..164a47a --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/phoenix + device domain 0 on end # domain +end # chip soc/amd/phoenix diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..927af2f --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies
by Eric Lai (Code Review) 10 Apr '23

10 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 ) Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/pci/pcie_gpp.c: https://review.coreboot.org/c/coreboot/+/74288/comment/4f039610_c3c0acc6 PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US > value used by AGESA/FSP (and has been unchanged for 5 years per commit history), I'll update the com […] Will this differ by platform? If so, Kconfig maybe better. -- To view, visit https://review.coreboot.org/c/coreboot/+/74288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4 Gerrit-Change-Number: 74288 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 Apr 2023 00:24:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/spi: Mmap 32M/64M flash
by Nico Huber (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74260 ) Change subject: soc/amd/spi: Mmap 32M/64M flash ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > For the newest SOC and 32M or 64M SPI flash. I meant more, where will the mmap API be called? AIUI, the current implementation will only work in very simple cases, i.e. a single mapping at a time. While the API currently allows things like this: const struct region_device *rd = boot_device_ro(); void *a = rdev_mmap(rd, 0, 1234); void *b = rdev_mmap(rd, 34567890, 1234); memcmp(a, b, 1234); Such uses are not possible with the one-mapping-at-a-time SPI_ROM_PAGE register. We also leak mappings of boot_device_ro() on purpose, because the mapping is expected to work indefinitely. For instance elog_flash_offset_to_address(), or spi_flash_get_mmap_windows(). These are expected to be used by the payload and OS without knowing any SPI_ROM_PAGE index. To be fully compatible with existing uses of boot_device_ro(), I would investigate if working on a copy is feasible for `index != 0`, i.e. allocate memory when `.mmap` gets called and pre-fill it with the data at the given offset. -- To view, visit https://review.coreboot.org/c/coreboot/+/74260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2bf1390635494443cac9ee8600a4a741a78c0d Gerrit-Change-Number: 74260 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 09 Apr 2023 22:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: drivers/efi: Fix linker error when SMM phase uses option API
by Lean Sheng Tan (Code Review) 09 Apr '23

09 Apr '23

Attention is currently required from: Benjamin Doron, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73905 ) Change subject: drivers/efi: Fix linker error when SMM phase uses option API ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: will let Arthur comments on this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/73905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief3b52965d8fde141c12266a716f254dd45559d5 Gerrit-Change-Number: 73905 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 09 Apr 2023 20:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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