coreboot-gerrit April 2023

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[S] Change in coreboot[master]: intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74350 ) Change subject: intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/pch/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc D src/southbridge/intel/common/madt.c M src/southbridge/intel/lynxpoint/Kconfig 6 files changed, 19 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 63f0439..bd1bea5 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -4,6 +4,7 @@ config PCH_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS @@ -17,7 +18,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_LYNXPOINT_LP select RTC - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index a0d8605..5ba913d 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -10,6 +10,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS @@ -34,7 +35,6 @@ select RTC select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_SMM - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select TCO_SPACE_NOT_YET_SPLIT diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index 0caf964..2da6971 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -61,9 +61,6 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_PMBASE -config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT - bool - config SOUTHBRIDGE_INTEL_COMMON_FINALIZE bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index fe61af1..2f4c777 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -50,8 +50,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c - smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c deleted file mode 100644 index 2482391..0000000 --- a/src/southbridge/intel/common/madt.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 9cea74b..af346ab 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS @@ -14,7 +15,6 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE -- To view, visit https://review.coreboot.org/c/coreboot/+/74350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Gerrit-Change-Number: 74350 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: sb/intel: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74349 ) Change subject: sb/intel: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... sb/intel: Use ACPI_COMMON_MADT_IOAPIC i82801gx, i82801ix, i82801jx: Maintain IRQ #0 to GSI #2 override as positive edge trigger. ibexpeak, emulation/qemu-q35: Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/Makefile.inc D src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc D src/southbridge/intel/ibexpeak/madt.c 11 files changed, 24 insertions(+), 78 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index a20092f..3105069 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -14,7 +14,6 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MEMORY_MAPPED_TPM select MAINBOARD_HAS_CHROMEOS - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select BOOT_DEVICE_NOT_SPI_FLASH select BOOT_DEVICE_MEMORY_MAPPED diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 330915f..2467e39 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 2871453..cacfbfb 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -349,20 +349,6 @@ i82801gx_fixups(dev); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - return current; -} - static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index d93afa6..fb33474 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 0000913..8db30ad 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -22,10 +22,6 @@ smm-y += smihandler.c -ifneq ($(CONFIG_BOARD_EMULATION_QEMU_X86_Q35),y) -ramstage-y += madt.c -endif - CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include endif diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c deleted file mode 100644 index 1ac8149..0000000 --- a/src/southbridge/intel/i82801ix/madt.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - return current; -} diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 62684ec..3f0ab10 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 8ff7926..e93502f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -379,20 +379,6 @@ i82801jx_set_acpi_mode(dev); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - - return current; -} - static void i82801jx_lpc_read_resources(struct device *dev) { int i, io_index = 0; diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ffeef5d..adc3842 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -7,6 +7,7 @@ config SOUTH_BRIDGE_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index b81792b..99968f8 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -20,7 +20,6 @@ ramstage-y += ../bd82x6x/me_status.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c -ramstage-y += madt.c smm-y += smihandler.c diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c deleted file mode 100644 index c5b1f0b..0000000 --- a/src/southbridge/intel/ibexpeak/madt.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/ioapic.h> -#include <acpi/acpi.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, - MP_IRQ_POLARITY_DEFAULT | - MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); - - return current; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/74349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a Gerrit-Change-Number: 74349 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74348 ) Change subject: ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT ...................................................................... ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms' implementations of adding IOAPIC and IRQ override entries for ACPI MADT tables. Platforms that have a more complex MADT may continue to add custom entries using CUSTOM_ACPI_MADT. Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/mainboard/asus/p2b/Kconfig M src/soc/intel/quark/Kconfig 4 files changed, 51 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 5af8b22..3b02070 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -31,13 +31,22 @@ Set to indicate <soc/nvs.h> exists for the platform with a definition for global_nvs. +config ACPI_CUSTOM_MADT + bool + default n if ACPI_NO_CUSTOM_MADT + default y + help + Selected by platforms that need to expose custom MADT entries. + +config ACPI_NO_CUSTOM_MADT + bool + default y if ACPI_COMMON_MADT_LAPIC && ACPI_COMMON_MADT_IOAPIC + config ACPI_COMMON_MADT_LAPIC bool -config ACPI_NO_MADT +config ACPI_COMMON_MADT_IOAPIC bool - help - Selected by platforms that don't expose a useful MADT. config ACPI_NO_PCAT_8259 bool diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index c357e2b..e06ac47 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -276,6 +276,18 @@ return irqoverride->length; } +static unsigned long acpi_create_madt_ioapic_gsi0_default(unsigned long current) +{ + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); + + current += acpi_create_madt_irqoverride((void *)current, MP_BUS_ISA, 0, 2, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH); + + current += acpi_create_madt_sci_override((void *)current); + + return current; +} + static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { @@ -353,7 +365,10 @@ if (CONFIG(ACPI_COMMON_MADT_LAPIC)) current = acpi_create_madt_lapics_with_nmis(current); - if (!CONFIG(ACPI_NO_MADT)) + if (CONFIG(ACPI_COMMON_MADT_IOAPIC)) + current = acpi_create_madt_ioapic_gsi0_default(current); + + if (CONFIG(ACPI_CUSTOM_MADT)) current = acpi_fill_madt(current); /* (Re)calculate length and checksum. */ diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 986cfde..a645bcc 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ACPI_NO_MADT + select ACPI_NO_CUSTOM_MADT select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 58f01da..631755c 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -9,7 +9,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ACPI_NO_MADT + select ACPI_NO_CUSTOM_MADT select ARCH_X86 select NO_ECAM_MMCONF_SUPPORT select NO_SMM -- To view, visit https://review.coreboot.org/c/coreboot/+/74348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Gerrit-Change-Number: 74348 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74348 ) Change subject: ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT ...................................................................... Patch Set 4: (1 comment) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/74348/comment/f9414543_abadc0d0 PS4, Line 47: : config ACPI_COMMON_MADT_IOAPIC : bool > Well it's not a visible option. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Gerrit-Change-Number: 74348 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 26 Apr 2023 11:02:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in qc_blobs[master]: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes f...
by Bharath N (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Shelley Chen, Paul Menzel, Julius Werner. Bharath N has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/73955 ) Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 50 to 69 ...................................................................... Patch Set 1: (1 comment) File sc7180/qtiseclib/Release_Notes.txt: https://review.coreboot.org/c/qc_blobs/+/73955/comment/7ab28657_c6207c9f PS1, Line 5: Version : 00069 > Okay, can you please open an internal bug with us, explain the issue in detail and point at the exac […] please find internal bug - https://partnerissuetracker.corp.google.com/issues/279558372 we have created CL for above bug - https://chrome-internal-review.googlesource.com/c/chromeos/vendor/qcseclib/… -- To view, visit https://review.coreboot.org/c/qc_blobs/+/73955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I55506e35b6312a7d0d5b2e9da721a377f6e196bc Gerrit-Change-Number: 73955 Gerrit-PatchSet: 1 Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Name of user not set #1004463 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 26 Apr 2023 10:54:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Bharath N <quic_bharn(a)quicinc.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86/ioapic: Promote ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74337 ) Change subject: arch/x86/ioapic: Promote ioapic_get_sci_pin() ...................................................................... arch/x86/ioapic: Promote ioapic_get_sci_pin() Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/quark/lpc.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 28 files changed, 72 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a2865cb..c357e2b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -226,7 +226,7 @@ } #endif -u16 acpi_sci_int(void) +static u16 acpi_sci_int(void) { #if ENV_X86 u8 gsi, irq, flags; @@ -1736,6 +1736,8 @@ if (CONFIG(USE_PC_CMOS_ALTCENTURY)) fadt->century = RTC_CLK_ALTCENTURY; + fadt->sci_int = acpi_sci_int(); + arch_fill_fadt(fadt); acpi_fill_fadt(fadt); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 2c8f2ef..78a6005 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1345,8 +1345,6 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current); -u16 acpi_sci_int(void); - int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 0d2c517..7a64c11 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -49,8 +49,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 09c35db..1fbff53 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,6 +16,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/iomap.h> #include <amdblocks/lpc.h> +#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/southbridge.h> @@ -34,6 +35,13 @@ pm_write8(PM_SERIRQ_CONF, byte); } +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; +} + static void fch_ioapic_init(void) { fch_enable_ioapic_decode(); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 2943d7d..d97dc09 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -52,8 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 8fb7237..94cb246 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -51,8 +51,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index ea2a997..427fb74 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -52,8 +52,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 341d9e0..5d34f47 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -56,8 +56,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 39f13b6..9aef608 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -50,8 +50,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - fadt->sci_int = ACPI_SCI_IRQ; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index a76d161..c01a79a 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <cpu/x86/smm.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> #include "chip.h" @@ -11,8 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index a76d161..d071b92 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,8 +11,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 9355670..2ffebc3 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -10,8 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = 9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 1ddee34..9aaca21 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -36,6 +36,15 @@ register_new_ioapic_gsi0(VIO_APIC_VADDR); } +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; +} + static void enable_hpet(struct device *dev) { size_t i; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 50854fa..1b5538f 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -94,8 +94,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_int(); - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index 92b7249..115a7b9 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/iomap.h> @@ -34,6 +35,13 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +/* Implemented just to fill FADT SCI_INT as 0. */ +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *irq = 0; + *gsi = 0; +} + static struct device_operations device_ops = { .read_resources = pmc_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 1865d36..fe65fb2 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -25,8 +25,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - if (permanent_smi_handler()) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index e202824..231766b 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -42,6 +42,8 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_SCI_IRQ 9 + #define ACPI_SMI_CTL_PORT 0xb2 #define ACPI_SMI_CMD_CST_CONTROL 0xde #define ACPI_SMI_CMD_PST_CONTROL 0xad diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 2dc2ae3..593f548 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -19,6 +19,13 @@ * HUDSON enables SATA by default in SMBUS Control. */ +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW; +} + static void sm_init(struct device *dev) { register_new_ioapic_gsi0(VIO_APIC_VADDR); diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index 296ee2b..31f2a06 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..872d994 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <assert.h> #include <bootmode.h> #include <device/pci_ops.h> @@ -92,3 +93,12 @@ return acpi_get_sleep_type() == ACPI_S3; } + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; +} diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index d83925d..66ae2bb 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -16,8 +16,6 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - fadt->sci_int = 9; - if (permanent_smi_handler()) { /* TODO: SMI handler is not implemented. */ fadt->smi_cmd = 0x00; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index c5329f4..7d86e8a 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -67,6 +67,15 @@ } } +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) +{ + *gsi = ACPI_SCI_IRQ; + *irq = ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; +} + static void sb_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 5b01948..5015659 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -8,8 +8,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 3f97145..7cdd631 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -13,8 +13,6 @@ struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 78443ea..92fece2 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -9,8 +9,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index f0f4ca1..a2defd2 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -9,8 +9,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index dfb9774..a917fb8 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index a90d0a8..ee7b309 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -12,8 +12,6 @@ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); - fadt->sci_int = 0x9; - if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/74337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Gerrit-Change-Number: 74337 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel: Introduce ioapic_get_sci_pin()
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74326 ) Change subject: soc/intel: Introduce ioapic_get_sci_pin() ...................................................................... soc/intel: Introduce ioapic_get_sci_pin() According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/arch/x86/include/arch/ioapic.h M src/include/acpi/acpi.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/common/block/acpi/acpi.c 10 files changed, 131 insertions(+), 92 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2540929..a2865cb 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -17,6 +17,7 @@ #include <acpi/acpi_ivrs.h> #include <acpi/acpigen.h> #include <arch/hpet.h> +#include <arch/smp/mpspec.h> #include <cbfs.h> #include <cbmem.h> #include <commonlib/helpers.h> @@ -225,6 +226,24 @@ } #endif +u16 acpi_sci_int(void) +{ +#if ENV_X86 + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags); + + /* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */ + if (!CONFIG(ACPI_HAVE_PCAT_8259)) + return gsi; + + assert(irq < 16); + return irq; +#else + return 0; +#endif +} + int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { @@ -238,6 +257,25 @@ return irqoverride->length; } +int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride) +{ + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags); + + if (!CONFIG(ACPI_HAVE_PCAT_8259)) + irq = gsi; + + irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ + irqoverride->length = sizeof(acpi_madt_irqoverride_t); + irqoverride->bus = MP_BUS_ISA; + irqoverride->source = irq; + irqoverride->gsirq = gsi; + irqoverride->flags = flags; + + return irqoverride->length; +} + static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint) { diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 6c5282b..9dc2339 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -22,6 +22,8 @@ void register_new_ioapic_gsi0(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif #endif diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 58db58c..2c8f2ef 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1338,12 +1338,15 @@ int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); +int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride); unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current); +u16 acpi_sci_int(void); + int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1c6023d..dce55af 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -10,7 +10,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> @@ -52,14 +51,21 @@ } }; -int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; /* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -76,13 +82,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } static acpi_tstate_t soc_tss_table[] = { @@ -280,33 +288,14 @@ acpigen_write_processor_cnot(pattrs->num_cpus); } -static unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current = acpi_madt_irq_overrides(current); + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + current += acpi_create_madt_sci_override((void *)current); return current; } diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index b747db7..db07de1 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -5,6 +5,4 @@ #include <acpi/acpi.h> -int acpi_sci_irq(void); - #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1927421..0ea54b8 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -81,14 +81,21 @@ gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; } -int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; /* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -105,13 +112,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } static acpi_tstate_t soc_tss_table[] = { @@ -309,33 +318,14 @@ acpigen_write_processor_cnot(pattrs->num_cpus); } -static unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); - - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current = acpi_madt_irq_overrides(current); + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + current += acpi_create_madt_sci_override((void *)current); return current; } diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index ccb48eb..fa4c804 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -5,7 +5,6 @@ #include <acpi/acpi.h> -int acpi_sci_irq(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index cfc15a8..50854fa 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -24,9 +24,11 @@ #define CPUID_6_EAX_ISST (1 << 7) -static int acpi_sci_irq(void) +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { - int sci_irq = 9; + int sci_irq = ACPI_SCI_IRQ; uint32_t scis; scis = soc_read_sci_irq_select(); @@ -47,31 +49,17 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; } - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); } -static unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - - flags |= soc_madt_sci_irq_polarity(sci); - - /* SCI */ - current += - acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - - return current; -} static const uintptr_t default_ioapic_bases[] = { IO_APIC_ADDR }; @@ -95,14 +83,18 @@ for (int i = 0; i < ioapic_entries; i++) current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); - return acpi_madt_irq_overrides(current); + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + current += acpi_create_madt_sci_override((void *)current); + + return current; } void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int(); if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/74326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Gerrit-Change-Number: 74326 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: ACPI: Add acpigen_write_PTC()
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74473 ) Change subject: ACPI: Add acpigen_write_PTC() ...................................................................... ACPI: Add acpigen_write_PTC() Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 34 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index d308930..d613bec 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -711,7 +711,7 @@ acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } -void acpigen_write_empty_PTC(void) +void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt) { /* Name (_PTC, Package (0x02) @@ -719,31 +719,35 @@ ResourceTemplate () { Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address + 0x00, // Duty Width + 0x00, // Duty Offset + 0x0000000000000000, // P_CNT IO Address ,) }, ResourceTemplate () { Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address + 0x00, // Duty Width + 0x00, // Duty Offset + 0x0000000000000000, // P_CNT IO Address ,) } }) */ acpi_addr_t addr = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 0, - .bit_offset = 0, + .bit_width = duty_width, + .bit_offset = duty_offset, .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0, + .addrl = p_cnt, .addrh = 0, }; + if (addr.addrl != 0) + addr.space_id = ACPI_ADDRESS_SPACE_IO; + else + addr.space_id = ACPI_ADDRESS_SPACE_FIXED; + acpigen_write_name("_PTC"); acpigen_write_package(2); @@ -756,6 +760,11 @@ acpigen_pop_len(); } +void acpigen_write_empty_PTC(void) +{ + acpigen_write_PTC(0, 0, 0); +} + static void __acpigen_write_method(const char *name, uint8_t flags) { acpigen_emit_byte(METHOD_OP); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index ae50143..180e937 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -431,6 +431,7 @@ void acpigen_write_PPC_NVS(void); void acpigen_write_empty_PCT(void); void acpigen_write_empty_PTC(void); +void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt); void acpigen_write_PRW(u32 wake, u32 level); void acpigen_write_STA(uint8_t status); void acpigen_write_STA_ext(const char *namestring); -- To view, visit https://review.coreboot.org/c/coreboot/+/74473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Gerrit-Change-Number: 74473 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: cpu/intel/speedstep: Separate single SSDT CPU entry
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74400 ) Change subject: cpu/intel/speedstep: Separate single SSDT CPU entry ...................................................................... cpu/intel/speedstep: Separate single SSDT CPU entry Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/speedstep/acpi.c M src/southbridge/intel/i82371eb/acpi_tables.c 2 files changed, 70 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 0d2cc87..0a13445 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -70,53 +70,61 @@ return SW_ANY; } +static void generate_cpu_entry(int cpu, int core, int cores_per_package) +{ + int pcontrol_blk = PMB0_BASE, plen = 6; + + static struct { + int once; + uint8_t coordination; + int num_cstates; + const acpi_cstate_t *cstates; + sst_table_t pstates; + } s; + + if (!s.once) { + s.once = 1; + s.coordination = get_p_state_coordination(); + s.num_cstates = get_cst_entries(&s.cstates); + speedstep_gen_pstates(&s.pstates); + } + + if (core > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx. */ + acpigen_write_processor(cpu * cores_per_package + core, pcontrol_blk, plen); + + /* Generate p-state entries. */ + gen_pstate_entries(&s.pstates, cpu, cores_per_package, s.coordination); + + /* Generate c-state entries. */ + if (s.num_cstates > 0) + acpigen_write_CST_package(s.cstates, s.num_cstates); + + acpigen_pop_len(); +} + /** * @brief Generate ACPI entries for Speedstep for each cpu */ void generate_cpu_entries(const struct device *device) { - int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); - int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; - int numcpus = totalcores/cores_per_package; /* This assumes that all - CPUs share the same - layout. */ + int cores_per_package = (cpuid_ebx(1) >> 16) & 0xff; - int num_cstates; - const acpi_cstate_t *cstates; - sst_table_t pstates; - uint8_t coordination = get_p_state_coordination(); + /* This assumes that all CPUs share the same layout. */ + int numcpus = totalcores / cores_per_package; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - num_cstates = get_cst_entries(&cstates); - speedstep_gen_pstates(&pstates); + for (int cpu_id = 0; cpu_id < numcpus; ++cpu_id) + for (int core_id = 0; core_id < cores_per_package; core_id++) + generate_cpu_entry(cpu_id, core_id, cores_per_package); - for (cpuID = 0; cpuID < numcpus; ++cpuID) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx. */ - acpigen_write_processor( - cpuID * cores_per_package + coreID - 1, - pcontrol_blk, plen); - - /* Generate p-state entries. */ - gen_pstate_entries(&pstates, cpuID, - cores_per_package, coordination); - - /* Generate c-state entries. */ - if (num_cstates > 0) - acpigen_write_CST_package( - cstates, num_cstates); - - acpigen_pop_len(); - } - } /* PPKG is usually used for thermal management of the first and only package. */ acpigen_write_processor_package("PPKG", 0, cores_per_package); diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index cd002e8..a4cd1b3 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -6,18 +6,27 @@ #include <device/device.h> #include "i82371eb.h" +static void generate_cpu_entry(int cpu) +{ + int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6; + + acpigen_write_processor(cpu, pcontrol_blk, plen); + acpigen_pop_len(); +} + void generate_cpu_entries(const struct device *device) { - int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; + int cpu; int numcpus = dev_count_cpu(); + printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); /* without the outer scope, further ssdt addition will end up * within the processor statement */ acpigen_write_scope("\\_SB"); - for (cpu=0; cpu < numcpus; cpu++) { - acpigen_write_processor(cpu, pcontrol_blk, plen); - acpigen_pop_len(); - } + + for (cpu = 0; cpu < numcpus; cpu++) + generate_cpu_entry(cpu); + acpigen_pop_len(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Gerrit-Change-Number: 74400 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Make ramtop offset configurable
by Subrata Banik (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Sean Rhodes, Dinesh Gehlot, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74511 ) Change subject: soc/intel/common: Make ramtop offset configurable ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: I will test this CL on Rex (MTL) and get back -- To view, visit https://review.coreboot.org/c/coreboot/+/74511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Gerrit-Change-Number: 74511 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 10:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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