coreboot-gerrit April 2023

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit
by Subrata Banik (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Andrey Petrov. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74784 ) Change subject: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit ...................................................................... drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit This patch calls into fsp_get_pch_reset_status() to get the MultiPhaseSiInit API return status if FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN is enabled. Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function can be considered as an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Any SoC platform that selects the FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/74784/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 678892a..9505e1d 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -10,6 +10,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <program_loading.h> +#include <soc/intel/common/reset.h> #include <soc/intel/common/vbt.h> #include <stage_cache.h> #include <string.h> @@ -194,6 +195,8 @@ multi_phase_params.phase_index = i; multi_phase_params.multi_phase_param_ptr = NULL; status = multi_phase_si_init(&multi_phase_params); + if (CONFIG(FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN)) + status = fsp_get_pch_reset_status(); fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status); } timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END); -- To view, visit https://review.coreboot.org/c/coreboot/+/74784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa Gerrit-Change-Number: 74784 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 26 Apr '23

26 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74783 ) Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... soc/intel/common: Introduce API to get the FSP Reset Status This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae --- M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h 2 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74783/1 diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index bf265515..d6319f0 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -1,10 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> #include <stdint.h> +static const uint8_t fsp_reset_guid[16] = { + 0xff, 0x97, 0x05, 0xea, 0x58, 0x88, 0xca, 0x41, + 0xbb, 0xc1, 0xfe, 0x18, 0xfc, 0xd2, 0x8e, 0x22 +}; + +static const uint8_t fsp_global_reset_guid[16] = { + 0x4c, 0x1b, 0xb3, 0x9d, 0xef, 0xf5, 0xbb, 0x48, + 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 +}; + +/* Platform Reset String as per Intel FSP is "PCH RESET" in unicode */ +#define PLATFORM_RESET_STRING_LENGTH 20 + +struct pch_reset_data { + char reserved[PLATFORM_RESET_STRING_LENGTH]; + efi_guid_t global_reset_uid; +}; + +/* This structure is used to provide information about PCH Reset */ +struct fsp_reset_hob { + EFI_RESET_TYPE reset_type; + struct pch_reset_data reset_data; +}; + void chipset_handle_reset(uint32_t status) { if (status == CONFIG_FSP_STATUS_GLOBAL_RESET) { @@ -15,3 +40,29 @@ printk(BIOS_ERR, "unhandled reset type %x\n", status); die("unknown reset type"); } + +/* + * Return PCH Reset Status + * The return status can be between EfiResetCold, EfiResetWarm, EfiResetShutdown + * or EfiResetPlatformSpecific. + * + * If reset type if `EfiResetPlatformSpecific` then relying on pch_reset_data structure + * to know if th reset type is a global reset. + */ +uint32_t fsp_get_pch_reset_status(void) +{ + if (!CONFIG(FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN)) + return 0; + + size_t size = 0; + const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); + if (!hob) + return 0; + + if ((hob->reset_type == EfiResetPlatformSpecific) && + fsp_guid_compare((void *)&(hob->reset_data.global_reset_uid), + fsp_global_reset_guid)) + return CONFIG_FSP_STATUS_GLOBAL_RESET; + + return hob->reset_type; +} diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index e1f6aab..df541c8 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -13,4 +13,14 @@ /* Prepare for reset, run do_global_reset(), halt. */ __noreturn void global_reset(void); +/* + * Return PCH Reset Status + * The return status can be between EfiResetCold, EfiResetWarm, EfiResetShutdown + * or EfiResetPlatformSpecific. + * + * If reset type if `EfiResetPlatformSpecific` then relying on pch_reset_data structure + * to know if th reset type is a global reset. + */ +uint32_t fsp_get_pch_reset_status(void); + #endif /* _INTEL_COMMON_RESET_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Create config option to handle broken FSP API
by Subrata Banik (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Andrey Petrov. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74782 ) Change subject: drivers/intel/fsp2_0: Create config option to handle broken FSP API ...................................................................... drivers/intel/fsp2_0: Create config option to handle broken FSP API This patch applies a workaround to fix an issue where FSP MultiPhaseSIInit API is unable to return the ERROR status to the bootloader upon exiting. As a result, it affects the platform stability where silicon reference code is expecting a reset (warm/cold/global) to complete the chipset initialization process but unfortunately as bootloader is unable to understand the return status in proper, it failed to take required action to meet the silicon reference code requirement. This patch is the base code which just adds the config option to allow the target SoC platform to apply this W/A if the problem existed inside the FSP MultiPhaseSiInit. At present the problem has only been reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. ADL/RPL FSP is already in the post PV phase where the ETA to fix problems properly inside the FSP is not known. Additionally, MTL FSP doesn't exhibit this problem hence, most likely this solution is only for ADL/RPL SoC based platform. BUG=b:278665768 TEST=No functional impact as this patch just added the config option. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3b15ef5b50fe1fe73bf9ad0aa4be90aae07ebf73 --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74782/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2132737..378f4fb 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -389,4 +389,17 @@ Save MRC training data after FSP-S. Select this on platforms that generate MRC cache HOB data as part of FSP-S rather than FSP-M. +config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN + bool + default n + depends on PLATFORM_USES_FSP2_2 + help + Select this config for Intel SoC platform where FSP MultiPhaseSiInit API is unable + to return ERROR status properly. + + The config option will be selected based on the target SoC platform and if the + problem existed inside the FSP MultiPhaseSiInit. At present the problem has only + reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable + to return any ERROR status. + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b15ef5b50fe1fe73bf9ad0aa4be90aae07ebf73 Gerrit-Change-Number: 74782 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Inject newline after printing EFI GUID
by Subrata Banik (Code Review) 26 Apr '23

26 Apr '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74781 ) Change subject: drivers/intel/fsp2_0: Inject newline after printing EFI GUID ...................................................................... drivers/intel/fsp2_0: Inject newline after printing EFI GUID TEST=fsp_print_guid() output doesn't get cobbled with other serial output and now separated by a newline character. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8d47dbc5d493f86f14a1bbcf9cb5c16c0e12b841 --- M src/drivers/intel/fsp2_0/hand_off_block.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74781/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 1e7551c..0e6a39f 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -205,7 +205,7 @@ mid[0] = read16(id + 4); mid[1] = read16(id + 6); - printk(level, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + printk(level, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x\n", big, mid[0], mid[1], id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d47dbc5d493f86f14a1bbcf9cb5c16c0e12b841 Gerrit-Change-Number: 74781 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74359 ) Change subject: AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74359 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/southbridge/amd/pi/hudson/Kconfig 2 files changed, 16 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index e139639..5cf275b 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -6,20 +6,8 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* TODO: Remove the hardcode */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - return current; } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 4b19431..6a3d61d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -10,7 +10,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_CUSTOM_MADT select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE -- To view, visit https://review.coreboot.org/c/coreboot/+/74359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a Gerrit-Change-Number: 74359 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74358 ) Change subject: soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC For the first IOAPIC, use the common MADT generator with default IRQ overrides. Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 23 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 8f4e308..c750e7e 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -1,7 +1,9 @@ config SOC_INTEL_COMMON_BLOCK_ACPI depends on SOC_INTEL_COMMON_BLOCK_CPU depends on SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + select ACPI_CUSTOM_MADT bool help Intel Processor common code for ACPI diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 1b5538f..fda82d4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -80,12 +80,12 @@ /* IOAPIC */ ioapic_entries = soc_get_ioapic_info(&ioapic_table); - for (int i = 0; i < ioapic_entries; i++) - current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - current += acpi_create_madt_sci_override((void *)current); + /* Default SOC IOAPIC entry */ + ASSERT(ioapic_table[0] == IO_APIC_ADDR); + + for (int i = 1; i < ioapic_entries; i++) + current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Gerrit-Change-Number: 74358 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74354 ) Change subject: soc/amd: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... soc/amd: Use ACPI_COMMON_MADT_IOAPIC Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74354 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c 7 files changed, 19 insertions(+), 61 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 7a64c11..732e736 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -21,19 +21,10 @@ unsigned long acpi_fill_madt(unsigned long current) { - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); return current; diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 289efbc..9355f7d 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -2,7 +2,9 @@ bool depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO select ACPI_AMD_HARDWARE_SLEEP_VALUES + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_CUSTOM_MADT help Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index d97dc09..f5185d4 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -24,19 +24,9 @@ unsigned long acpi_fill_madt(unsigned long current) { - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); return current; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 94cb246..a8b04bf 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -23,19 +23,9 @@ unsigned long acpi_fill_madt(unsigned long current) { - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); return current; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 427fb74..e011571 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -24,19 +24,9 @@ unsigned long acpi_fill_madt(unsigned long current) { - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); return current; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 5d34f47..9e74c6e 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -27,20 +27,9 @@ unsigned long acpi_fill_madt(unsigned long current) { - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - current = acpi_fill_madt_irqoverride(current); return current; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 9aef608..7be76c1 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,19 +26,8 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Write Kern IOAPIC, only one */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); - /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, 0, 2, - MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); - /* SCI IRQ type override */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, - MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696 Gerrit-Change-Number: 74354 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74353 ) Change subject: asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC For uni-processor platforms, with SMP=n or MAX_CPUS=1, neither the LAPIC or IOAPIC MADT entries are added. Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-i440fx/Kconfig D src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/southbridge/intel/i82371eb/Kconfig 3 files changed, 19 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 5bf95b2..f02c92d 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -2,7 +2,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ACPI_COMMON_MADT_LAPIC select CPU_QEMU_X86 select NO_ECAM_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c deleted file mode 100644 index 593cbc7..0000000 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> - -#include "fw_cfg.h" -#include "acpi.h" - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 03e70a6..3f84668 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,4 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB + select ACPI_COMMON_MADT_IOAPIC if SMP + select ACPI_COMMON_MADT_LAPIC if SMP + select ACPI_NO_CUSTOM_MADT select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC -- To view, visit https://review.coreboot.org/c/coreboot/+/74353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361 Gerrit-Change-Number: 74353 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74352 ) Change subject: aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPIC ...................................................................... aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPIC IRQ override from IRQ #0 to GSI #2 is changed from MP_BUS_EISA to MP_BUS_ISA. Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/aopen/dxplplusu/Kconfig M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/southbridge/intel/i82801dx/Kconfig 3 files changed, 18 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 5c0ca2b..7d374f4 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -2,6 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ACPI_CUSTOM_MADT select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7505 select SOUTHBRIDGE_INTEL_I82870 diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index ba9d3c8..e22b454 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -8,9 +8,6 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - /* Southbridge IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); - bdev = pcidev_on_root(2, 0); /* P64H2 Bus B IOAPIC */ if (bdev) @@ -28,11 +25,5 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); } - /* Map ISA IRQ 0 to IRQ 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); - - /* IRQ9 differs from ISA standard - ours is active high, level-triggered */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD); - return current; } diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 2be911d..8393f38 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_INTEL_I82801DX bool + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/74352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997 Gerrit-Change-Number: 74352 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74351 ) Change subject: soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC ...................................................................... soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c 4 files changed, 18 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 0f908b6..958af34 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index dce55af..f24fe7f 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -287,15 +287,3 @@ /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(pattrs->num_cpus); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - current += acpi_create_madt_sci_override((void *)current); - - return current; -} diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 8d540f3..f618118 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0ea54b8..a278e55 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -318,18 +318,6 @@ acpigen_write_processor_cnot(pattrs->num_cpus); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* IOAPIC */ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); - current += acpi_create_madt_sci_override((void *)current); - - return current; -} - unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac Gerrit-Change-Number: 74351 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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