coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
by Chris Wang (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jason Nien, Martin Roth. Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74790 ) Change subject: mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence ...................................................................... mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence set Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/74790/1 diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 2e32b28..d8603b7 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -114,6 +114,7 @@ # The unit is set to one per ms register "edp_panel_t8_ms" = "112" + register "edp_panel_t9_ms" = "8" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. -- To view, visit https://review.coreboot.org/c/coreboot/+/74790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Gerrit-Change-Number: 74790 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: update FSP parameters for eDP power sequence adjus...
by Chris Wang (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74789 ) Change subject: soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment ...................................................................... soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment Add UPD parameter for eDP power sequence adjustment. The edp_panel_t9_ms parameter is set for bloff to varybloff. BUG=b:271704149 TEST=Build; Verify the UPD was pass to system integrated table. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b --- M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/74789/1 diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 5eb7c41..f161038 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -179,6 +179,8 @@ /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ uint8_t edp_panel_t8_ms; + /* Set for eDP power sequence adjustment timing T9 (from bloff to varybloff). */ + uint8_t edp_panel_t9_ms; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index cea26a9..6582a7c 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -171,6 +171,7 @@ mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; + mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/74789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b Gerrit-Change-Number: 74789 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
by Chris Wang (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74788 ) Change subject: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP ...................................................................... vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 --- M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74788/1 diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index b3d6dc3..e2622dd 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -102,7 +102,8 @@ /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; - /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/74788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Gerrit-Change-Number: 74788 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms
by Chris Wang (Code Review) 26 Apr '23

26 Apr '23

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74787 ) Change subject: soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms ...................................................................... soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=none Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/fsp_m_params.c M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 4 files changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/74787/1 diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 4297f90..2e32b28 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -112,8 +112,8 @@ register "dxio_tx_vboost_enable" = "1" - # The unit is set to one per 4ms - register "pwr_on_vary_bl_to_blon" = "0x1c" + # The unit is set to one per ms + register "edp_panel_t8_ms" = "112" device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 774ce5e..5eb7c41 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -177,9 +177,8 @@ /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ union usb3_force_gen1 usb3_port_force_gen1; - /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to - one per 4ms*/ - uint8_t pwr_on_vary_bl_to_blon; + /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */ + uint8_t edp_panel_t8_ms; }; diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 453ce69..cea26a9 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -170,7 +170,7 @@ } mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; - mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; + mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index 391c64b..b3d6dc3 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -101,8 +101,8 @@ /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; - /** Offset 0x04E9**/ uint8_t pwr_on_vary_bl_to_blon; - /** Offset 0x04EA**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; + /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/74787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Gerrit-Change-Number: 74787 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Enable tis_plat_irq_status
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74286 ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/myst: Enable tis_plat_irq_status ...................................................................... mb/google/myst: Enable tis_plat_irq_status This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/tpm_tis.c 2 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index 40a41df..ffa462a 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -1,7 +1,11 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += tpm_tis.c romstage-y += gpio.c +romstage-y += tpm_tis.c + +verstage-y += tpm_tis.c smm-y += smihandler.c diff --git a/src/mainboard/google/myst/variants/baseboard/tpm_tis.c b/src/mainboard/google/myst/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000..d03158d --- /dev/null +++ b/src/mainboard/google/myst/variants/baseboard/tpm_tis.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <security/tpm/tis.h> +#include <gpio.h> + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(GPIO_84); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Gerrit-Change-Number: 74286 Gerrit-PatchSet: 21 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/myst: Configure WLAN
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74113 ) Change subject: mb/google/myst: Configure WLAN ...................................................................... mb/google/myst: Configure WLAN Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/bootblock.c A src/mainboard/google/myst/romstage.c M src/mainboard/google/myst/variants/baseboard/Makefile.inc M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 7 files changed, 83 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index ce99f6b..ae54f9c 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -12,6 +12,7 @@ select DISABLE_KEYBOARD_RESET_PIN select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c index e9d69e3..4404666 100644 --- a/src/mainboard/google/myst/bootblock.c +++ b/src/mainboard/google/myst/bootblock.c @@ -23,6 +23,9 @@ variant_tpm_gpio_table(&gpios, &num_gpios); gpio_configure_pads(gpios, num_gpios); + + variant_early_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/myst/romstage.c b/src/mainboard/google/myst/romstage.c new file mode 100644 index 0000000..fc3402a --- /dev/null +++ b/src/mainboard/google/myst/romstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/platform_descriptors.h> + +void mb_pre_fspm(FSP_M_CONFIG *mcfg) +{ + size_t num_base_gpios; + const struct soc_amd_gpio *base_gpios; + + baseboard_romstage_gpio_table(&base_gpios, &num_base_gpios); + gpio_configure_pads(base_gpios, num_base_gpios); +} diff --git a/src/mainboard/google/myst/variants/baseboard/Makefile.inc b/src/mainboard/google/myst/variants/baseboard/Makefile.inc index ba09623..40a41df 100644 --- a/src/mainboard/google/myst/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/myst/variants/baseboard/Makefile.inc @@ -2,4 +2,6 @@ ramstage-y += gpio.c +romstage-y += gpio.c + smm-y += smihandler.c diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index ae5f341..7adb365 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -86,7 +86,12 @@ device domain 0 on device ref gpp_bridge_2_1 on end # WWAN - device ref gpp_bridge_2_2 on end # WLAN + device ref gpp_bridge_2_2 on # WLAN + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device ref gpp_bridge_2_3 on end # SD device ref gpp_bridge_2_4 on end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 56b8143..3196354 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -179,7 +179,27 @@ /* GPIO configuration in bootblock */ static const struct soc_amd_gpio bootblock_gpio_table[] = { - /* TODO(b/275965982): Fill bootblock gpio configuration */ + /* Enable WLAN */ + /* WLAN_DISABLE */ + PAD_GPO(GPIO_156, LOW), +}; + +/* Early GPIO configuration */ +static const struct soc_amd_gpio early_gpio_table[] = { + /* WLAN_AUX_RST_L (ACTIVE LOW) */ + PAD_GPO(GPIO_38, LOW), + /* Power on WLAN */ + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_9, HIGH), +}; + +/* PCIE_RST needs to be brought high before FSP-M runs */ +static const struct soc_amd_gpio romstage_gpio_table[] = { + /* Deassert all AUX_RESET lines & PCIE_RST */ + /* WLAN_AUX_RST_L (ACTIVE LOW) */ + PAD_GPO(GPIO_38, HIGH), + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), }; static const struct soc_amd_gpio espi_gpio_table[] = { @@ -205,12 +225,24 @@ *gpio = base_gpio_table; } +__weak void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(romstage_gpio_table); + *gpio = romstage_gpio_table; +} + __weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(bootblock_gpio_table); *gpio = bootblock_gpio_table; } +__weak void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + *gpio = early_gpio_table; +} + void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(espi_gpio_table); diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 6ce35bb..a3fd355 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -16,9 +16,15 @@ /* This function provides base GPIO configuration table. */ void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings in romstage. */ +void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + /* This function provides GPIO init in bootblock. */ void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides early GPIO init in early bootblock or psp. */ +void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + /* This function provides GPIO settings for eSPI bus. */ void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); -- To view, visit https://review.coreboot.org/c/coreboot/+/74113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Gerrit-Change-Number: 74113 Gerrit-PatchSet: 46 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Make FADT entries for RTC/CMOS architectural
by Kyösti Mälkki (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Fred Reitberger, Tim Chu, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74601 ) Change subject: ACPI: Make FADT entries for RTC/CMOS architectural ...................................................................... Patch Set 2: (2 comments) File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/74601/comment/643267b0_6ec2e277 PS1, Line 32: #define RTC_CENTURY 0x48 > <drivers/pc80/mcXXX. […] Done File src/southbridge/amd/pi/hudson/fadt.c: https://review.coreboot.org/c/coreboot/+/74601/comment/273f2765_9fb16f5f PS1, Line 43: fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ > need to check Comments about 0x7d and 0x7e were wrong. 52740 Rev 3.06 - March 18, 2016 BKDG for AMD Family 16h Models 30h-3Fh Processors IO073_x0D RTC Date Alarm The name reference is for 0x72/0x73 access, but index 0x0d works through 0x70/0x71 too. -- To view, visit https://review.coreboot.org/c/coreboot/+/74601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Gerrit-Change-Number: 74601 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 26 Apr 2023 12:13:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... mb/google/myst: Enable PCIe devices in devicetree Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 3 files changed, 125 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Van Patten: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 9d3b15b..703b74b 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -1,11 +1,92 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +static const fsp_dxio_descriptor myst_dxio_descriptors[] = { + { /* WWAN */ + .engine_type = UNUSED_ENGINE, + .port_present = true, + .start_logical_lane = 13, + .end_logical_lane = 13, + .device_number = PCI_SLOT(WWAN_DEVFN), + .function_number = PCI_FUNC(WWAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + }, + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 14, + .end_logical_lane = 14, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 15, + .end_logical_lane = 15, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN1, + .turn_off_unused_lanes = true, + .link_hotplug = 3, + .clk_req = CLK_REQ1, + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 19, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN_MAX, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + }, +}; + +static const fsp_ddi_descriptor myst_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI/DP */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - Unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + }, +}; + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - /* TODO(b/276744321): Initialize DXIO and DDI descriptors */ + *dxio_descs = myst_dxio_descriptors; + *dxio_num = ARRAY_SIZE(myst_dxio_descriptors); + *ddi_descs = myst_ddi_descriptors; + *ddi_num = ARRAY_SIZE(myst_ddi_descriptors); } diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index e4a2841..ae5f341 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -73,7 +73,22 @@ .speed = I2C_SPEED_FAST, }" + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WWAN + register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD + register "gpp_clk_config[4]" = "GPP_CLK_OFF" # SOC_FP_BOOT0 GPIO + register "gpp_clk_config[5]" = "GPP_CLK_OFF" # WLAN_AUX_RST_L GPIO + register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works + device domain 0 on + device ref gpp_bridge_2_1 on end # WWAN + device ref gpp_bridge_2_2 on end # WLAN + device ref gpp_bridge_2_3 on end # SD + device ref gpp_bridge_2_4 on end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index d5c2513..6ce35bb 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,13 @@ #define __BASEBOARD_VARIANTS_H__ #include <gpio.h> +#include <platform_descriptors.h> +#include <soc/pci_devs.h> + +#define WWAN_DEVFN PCIE_GPP_2_1_DEVFN +#define WLAN_DEVFN PCIE_GPP_2_2_DEVFN +#define SD_DEVFN PCIE_GPP_2_3_DEVFN +#define NVME_DEVFN PCIE_GPP_2_4_DEVFN /* This function provides base GPIO configuration table. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 44 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Enable SD card
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74653 ) Change subject: mb/siemens/mc_ehl4: Enable SD card ...................................................................... mb/siemens/mc_ehl4: Enable SD card This mainboard has SD slot available and therefore it should be enabled. Use the same SD card configuration as for mc_ehl2 mainboard. Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb A src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c 3 files changed, 59 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc index 2b78a7a..d9050f0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc @@ -3,5 +3,6 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += mainboard.c all-$(CONFIG_NC_FPGA_POST_CODE) += post.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 0d1ae71..56cfc3b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -89,6 +89,8 @@ register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ @@ -171,6 +173,7 @@ device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC + device pci 1a.1 on end # SD device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c new file mode 100644 index 0000000..4584892 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <device/pci_ids.h> +#include <gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> + +#define HOSTCTRL2 0x3E +#define HOSTCTRL2_PRESET (1 << 15) +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 +#define SD_CAP_BYP_SDR50 (1 << 13) +#define SD_CAP_BYP_SDR104 (1 << 14) +#define SD_CAP_BYP_DDR50 (1 << 15) + +void variant_mainboard_final(void) +{ + struct device *dev; + + /* Limit SD card speed to DDR50 mode to avoid SDR104/SDR50 modes due to + layout limitations. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + clrsetbits32(res2mmio(res, SD_CAP_BYP_REG1, 0), + SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50, + SD_CAP_BYP_DDR50); + + /* Use preset driver strength from preset value registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020 Gerrit-Change-Number: 74653 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Switch RTC type and connection
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74652 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl4: Switch RTC type and connection ...................................................................... mb/siemens/mc_ehl4: Switch RTC type and connection This mainboard has the RTC RV-3028-C7 connected to the I2C1. TEST: - Console Log shows no errors for RV-3028-C7 during I2C1 init - Finalize device for I2C 00:52 shows correct date and time Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652 Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb 2 files changed, 37 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig index 21789d7..8a40072 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -2,7 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select DRIVERS_I2C_RX6110SA + select DRIVERS_I2C_RV3028C7 select DRIVER_INTEL_I210 select INTEL_LPSS_UART_FOR_CONSOLE select NC_FPGA_POST_CODE diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 5cc496f..0d1ae71 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -148,7 +148,20 @@ device pci 14.0 on end # USB3.1 xHCI device pci 15.0 off end # I2C0 - device pci 15.1 on end # I2C1 + device pci 15.1 on # I2C1 + # Enable external RTC chip + chip drivers/i2c/rv3028c7 + register "bus_speed" = "I2C_SPEED_STANDARD" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + register "bckup_sw_mode" = "BACKUP_SW_LEVEL" + register "cap_charge" = "CHARGE_OFF" + device i2c 0x52 on end # RTC RV3028-C7 + end + end device pci 16.0 hidden end # Management Engine Interface 1 @@ -168,25 +181,9 @@ device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1f.0 on end # eSPI Interface device pci 1f.2 hidden end # Power Management Controller - device pci 1f.4 on # SMBus - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "bus_speed" = "I2C_SPEED_STANDARD" - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Gerrit-Change-Number: 74652 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2023