coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Switch RTC type and connection
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74652 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl4: Switch RTC type and connection ...................................................................... mb/siemens/mc_ehl4: Switch RTC type and connection This mainboard has the RTC RV-3028-C7 connected to the I2C1. TEST: - Console Log shows no errors for RV-3028-C7 during I2C1 init - Finalize device for I2C 00:52 shows correct date and time Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652 Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb 2 files changed, 37 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig index 21789d7..8a40072 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -2,7 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select DRIVERS_I2C_RX6110SA + select DRIVERS_I2C_RV3028C7 select DRIVER_INTEL_I210 select INTEL_LPSS_UART_FOR_CONSOLE select NC_FPGA_POST_CODE diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 5cc496f..0d1ae71 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -148,7 +148,20 @@ device pci 14.0 on end # USB3.1 xHCI device pci 15.0 off end # I2C0 - device pci 15.1 on end # I2C1 + device pci 15.1 on # I2C1 + # Enable external RTC chip + chip drivers/i2c/rv3028c7 + register "bus_speed" = "I2C_SPEED_STANDARD" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + register "bckup_sw_mode" = "BACKUP_SW_LEVEL" + register "cap_charge" = "CHARGE_OFF" + device i2c 0x52 on end # RTC RV3028-C7 + end + end device pci 16.0 hidden end # Management Engine Interface 1 @@ -168,25 +181,9 @@ device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1f.0 on end # eSPI Interface device pci 1f.2 hidden end # Power Management Controller - device pci 1f.4 on # SMBus - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "bus_speed" = "I2C_SPEED_STANDARD" - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Gerrit-Change-Number: 74652 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust USB settings
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74651 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl4: Adjust USB settings ...................................................................... mb/siemens/mc_ehl4: Adjust USB settings Correct the USB settings, suitable for this mainboard. Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651 Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb 1 file changed, 21 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 52da98e..5cc496f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -20,9 +20,9 @@ }" # USB related UPDs - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # X125 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # X135 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # internal USB-OC register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused @@ -32,7 +32,7 @@ register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Port is not used register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used -- To view, visit https://review.coreboot.org/c/coreboot/+/74651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Gerrit-Change-Number: 74651 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74650 ) Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes ...................................................................... mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to '0'. On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig index ee725cc..21789d7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -22,7 +22,7 @@ config EARLY_PCI_BRIDGE_FUNCTION hex depends on NC_FPGA_POST_CODE - default 0x2 + default 0x0 config EARLY_PCI_MMIO_BASE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/74650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Gerrit-Change-Number: 74650 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/siemens/mc_ehl4: Adjust GPIOs
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74628 ) Change subject: mb/siemens/mc_ehl4: Adjust GPIOs ...................................................................... mb/siemens/mc_ehl4: Adjust GPIOs Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must be adjust according to the circuit diagram for this mainboard. Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c 1 file changed, 23 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c index ea814a0..9f1c77f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c @@ -8,24 +8,17 @@ /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ - PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */ + PAD_NC(GPP_B4, NONE), /* Not connected */ PAD_NC(GPP_B9, NONE), /* Not connected */ PAD_NC(GPP_B10, NONE), /* Not connected */ PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ PAD_NC(GPP_B14, NONE), /* Not connected */ - PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ + PAD_NC(GPP_B15, NONE), /* Not connected */ PAD_NC(GPP_B18, NONE), /* Not connected */ PAD_NC(GPP_B19, NONE), /* Not connected */ - PAD_NC(GPP_B20, NONE), /* Not connected */ - PAD_NC(GPP_B21, NONE), /* Not connected */ - PAD_NC(GPP_B22, NONE), /* Not connected */ PAD_NC(GPP_B23, NONE), /* Not connected */ /* Community 0 - GpioGroup GPP_T */ - PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */ - PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */ - PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ - PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */ @@ -37,7 +30,6 @@ PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */ PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */ PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */ - PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */ PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */ PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */ @@ -54,13 +46,9 @@ PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */ /* Community 1 - GpioGroup GPP_H */ - PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */ - PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */ - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */ PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */ @@ -68,52 +56,29 @@ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */ /* Community 1 - GpioGroup GPP_U */ - PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */ - PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */ - PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */ - PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */ PAD_NC(GPP_U12, NONE), /* Not connected */ PAD_NC(GPP_U13, NONE), /* Not connected */ PAD_NC(GPP_U16, NONE), /* Not connected */ PAD_NC(GPP_U17, NONE), /* Not connected */ PAD_NC(GPP_U18, NONE), /* Not connected */ - PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */ /* Community 2 - GpioGroup DSW */ PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */ PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */ PAD_NC(GPD7, NONE), /* Not connected */ + PAD_NC(GPD9, NONE), /* Not connected */ PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */ + PAD_NC(GPD11, NONE), /* Not connected */ /* Community 3 - GpioGroup GPP_S */ PAD_NC(GPP_S0, NONE), /* Not connected */ PAD_NC(GPP_S1, NONE), /* Not connected */ - /* Community 3 - GpioGroup GPP_A */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */ - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */ - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */ - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */ - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ - /* Community 4 - GpioGroup GPP_C */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ PAD_NC(GPP_C5, NONE), /* Not connected */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */ PAD_NC(GPP_C8, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */ @@ -139,20 +104,15 @@ /* Community 4 - GpioGroup GPP_E */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */ PAD_NC(GPP_E6, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ + PAD_NC(GPP_E18, NONE), /* Not connected */ + PAD_NC(GPP_E19, NONE), /* Not connected */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ PAD_NC(GPP_R1, NONE), /* Not connected */ - PAD_NC(GPP_R2, NONE), /* Not connected */ PAD_NC(GPP_R3, NONE), /* Not connected */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Gerrit-Change-Number: 74628 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Disable Tccold Handshake
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74737 ) Change subject: mb/google/brya/var/omnigul: Disable Tccold Handshake ...................................................................... mb/google/brya/var/omnigul: Disable Tccold Handshake The patch disables Tccold Handshake to prevent possible display flicker issue for Omnigul board. Please refer to Intel doc#723158 for more information. BUG=b:279539826 BRANCH=firmware-brya-14505.B TEST=Verify the build for Omnigul board Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/omnigul/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 760ee82..dd78eda 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -10,6 +10,10 @@ register "sagv" = "SaGv_Enabled" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "disable_dynamic_tccold_handshake" = "true" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/74737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Gerrit-Change-Number: 74737 Gerrit-PatchSet: 5 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71717 ) Change subject: mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree ...................................................................... mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/romstage_fsp_params.c M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/adl/variants/darp8/romstage.c M src/mainboard/system76/adl/variants/galp6/romstage.c 5 files changed, 15 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michał Kopeć: Looks good to me, approved diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 189faf6..d50a950 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -261,6 +261,7 @@ device ref p2sb on end device ref hda on subsystemid 0x1462 0x9d25 + register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_dsp_enable" = "0" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 707f871..9a18f13 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -57,7 +57,6 @@ memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented memupd->FspmConfig.SkipExtGfxScan = 0; - memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; memupd->FspmConfig.PchHdaSdiEnable[0] = 1; /* diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 8f668be..d469491 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -84,6 +84,7 @@ end device ref p2sb on end device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" register "pch_hda_idisp_codec_enable" = "1" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" diff --git a/src/mainboard/system76/adl/variants/darp8/romstage.c b/src/mainboard/system76/adl/variants/darp8/romstage.c index 3d6a5fb..e6cf37f 100644 --- a/src/mainboard/system76/adl/variants/darp8/romstage.c +++ b/src/mainboard/system76/adl/variants/darp8/romstage.c @@ -17,7 +17,6 @@ }; const bool half_populated = false; - mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; mupd->FspmConfig.DmiMaxLinkSpeed = 4; mupd->FspmConfig.GpioOverride = 0; diff --git a/src/mainboard/system76/adl/variants/galp6/romstage.c b/src/mainboard/system76/adl/variants/galp6/romstage.c index 3d6a5fb..e6cf37f 100644 --- a/src/mainboard/system76/adl/variants/galp6/romstage.c +++ b/src/mainboard/system76/adl/variants/galp6/romstage.c @@ -17,7 +17,6 @@ }; const bool half_populated = false; - mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; mupd->FspmConfig.DmiMaxLinkSpeed = 4; mupd->FspmConfig.GpioOverride = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/71717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Gerrit-Change-Number: 71717 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Update comment
by Felix Held (Code Review) 26 Apr '23

26 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74734 ) Change subject: soc/amd/phoenix/Kconfig: Update comment ...................................................................... soc/amd/phoenix/Kconfig: Update comment Fix copy-paste comment on closing endif Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74734 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/amd/phoenix/Kconfig 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 64617f9..48fd2a5 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -504,4 +504,4 @@ endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK -endif # SOC_AMD_REMBRANDT_BASE +endif # SOC_AMD_PHOENIX -- To view, visit https://review.coreboot.org/c/coreboot/+/74734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc Gerrit-Change-Number: 74734 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Sean Rhodes (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Christian Walter, Angel Pons, Maximilian Brune, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74122 ) Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > don’t Sean… that is another round of work 😆 One patch, one file and one Kconfig option. Easy -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 12:03:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: Disable C1E for RPL CPU
by Joey Peng (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, YH Lin, Subrata Banik, Nick Vaccaro. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74786 ) Change subject: mb/google/brya/var/taeko: Disable C1E for RPL CPU ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e4c74aa288f1c824c5e7ce83090cf61d7653183 Gerrit-Change-Number: 74786 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 11:57:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add option to disable C1E
by Joey Peng (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Paul Menzel, Nick Vaccaro. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Add option to disable C1E ...................................................................... Patch Set 7: (7 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/74727/comment/741266b6_b5d18774 PS6, Line 7: mb/google/brya/var/taeko:Disable > Please add a space after the colon (:). Fixed in relation chain CL. Patchset: PS7: > is this really a chromeos specific change? […] Hi Subrata, Since taeko has ADL SKUs and RPL SKUs, we would like to keep C1E enabled on ADL SKUs. From FspSUpd.dsc in rplfsp, I saw that C1E is enabled by default, so I think currently it is enabled on all RPL projects. File src/mainboard/google/brya/variants/taeko/variant.c: https://review.coreboot.org/c/coreboot/+/74727/comment/ef4d28ec_dddfebc5 PS6, Line 17: //Disable C1E for RPL CPU > Please add a space. Fixed in relation chain CL. https://review.coreboot.org/c/coreboot/+/74727/comment/3ab6e344_9d129f48 PS6, Line 21: Disabling > Disable […] Fixed in relation chain CL. https://review.coreboot.org/c/coreboot/+/74727/comment/29a61286_80f7a7ce PS6, Line 23: else if (cpu_id == CPUID_ALDERLAKE_R0) { > > else should follow close brace '}' […] Fixed in relation chain CL. https://review.coreboot.org/c/coreboot/+/74727/comment/04f191a0_48ddfbd8 PS6, Line 24: config->c1e = 1; > Is there a default value? Should it be set explicitly? The default value is 1. We added it here to make sure it doesn't set to 0 when it shouldn't. File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/74727/comment/3b64ae63_4646ae7d PS6, Line 685: /* Enable or Disable C1E : * Default is set to 1. : * Set to 0 in order to disable C1E : */ > Please use the recommended style for multiline comments. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 7 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 26 Apr 2023 11:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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