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[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73124 ) Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter ...................................................................... soc/amd/mendocino: Remove the SPL DPTC parameter The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb M src/mainboard/google/skyrim/variants/whiterun/overridetree.cb M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/root_complex.c 6 files changed, 25 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 698d8c3..c92131c 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -260,6 +260,7 @@ register "fast_ppt_limit_mW" = "30000" register "slow_ppt_time_constant_s" = "5" register "stapm_time_constant_s" = "275" + # Remove the sustained_power_limit_mW when STT is enabled register "sustained_power_limit_mW" = "15000" register "thermctl_limit_degreeC" = "100" register "vrm_current_limit_mA" = "28000" diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index 00c143b..b34e2e3 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -11,8 +11,6 @@ end chip soc/amd/mendocino - # Power table for tablet mode - register "sustained_power_limit_mW_tablet" = "12000" register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb index f2d7a75..65c3231 100644 --- a/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/whiterun/overridetree.cb @@ -35,7 +35,6 @@ register "fast_ppt_limit_mW" = "30000" register "slow_ppt_limit_mW" = "18000" register "slow_ppt_time_constant_s" = "7" - register "sustained_power_limit_mW" = "15000" register "stt_min_limit" = "7000" register "stt_m1" = "0x148" @@ -47,7 +46,6 @@ register "fast_ppt_limit_mW_B" = "20000" register "slow_ppt_limit_mW_B" = "13000" register "slow_ppt_time_constant_s_B" = "5" - register "sustained_power_limit_mW_B" = "10000" register "stt_min_limit_B" = "5000" register "stt_m1_B" = "0x11F" @@ -59,7 +57,6 @@ register "fast_ppt_limit_mW_C" = "30000" register "slow_ppt_limit_mW_C" = "22000" register "slow_ppt_time_constant_s_C" = "10" - register "sustained_power_limit_mW_C" = "15000" register "stt_min_limit_C" = "10000" register "stt_m1_C" = "0x1A4" @@ -71,7 +68,6 @@ register "fast_ppt_limit_mW_D" = "25000" register "slow_ppt_limit_mW_D" = "15000" register "slow_ppt_time_constant_s_D" = "8" - register "sustained_power_limit_mW_D" = "10000" register "stt_min_limit_D" = "8000" register "stt_m1_D" = "0x1C3" @@ -83,7 +79,6 @@ register "fast_ppt_limit_mW_E" = "22000" register "slow_ppt_limit_mW_E" = "15000" register "slow_ppt_time_constant_s_E" = "4" - register "sustained_power_limit_mW_E" = "12000" register "stt_min_limit_E" = "7000" register "stt_m1_E" = "0x114" @@ -96,7 +91,6 @@ register "fast_ppt_limit_mW_F" = "18000" register "slow_ppt_limit_mW_F" = "12000" register "slow_ppt_time_constant_s_F" = "2" - register "sustained_power_limit_mW_F" = "9000" register "stt_min_limit_F" = "5000" register "stt_m1_F" = "0x15C" diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index c9ac6fc..755f96f 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -35,7 +35,6 @@ register "fast_ppt_limit_mW" = "30000" register "slow_ppt_limit_mW" = "25000" register "slow_ppt_time_constant_s" = "5" - register "sustained_power_limit_mW" = "15000" register "stt_min_limit" = "15000" register "stt_m1" = "0x18F" @@ -47,7 +46,6 @@ register "fast_ppt_limit_mW_B" = "15000" register "slow_ppt_limit_mW_B" = "15000" register "slow_ppt_time_constant_s_B" = "5" - register "sustained_power_limit_mW_B" = "10500" register "stt_min_limit_B" = "10500" register "stt_m1_B" = "0x18F" @@ -59,7 +57,6 @@ register "fast_ppt_limit_mW_C" = "30000" register "slow_ppt_limit_mW_C" = "25000" register "slow_ppt_time_constant_s_C" = "5" - register "sustained_power_limit_mW_C" = "15000" register "stt_min_limit_C" = "15000" register "stt_m1_C" = "0x152" @@ -71,7 +68,6 @@ register "fast_ppt_limit_mW_D" = "15000" register "slow_ppt_limit_mW_D" = "15000" register "slow_ppt_time_constant_s_D" = "5" - register "sustained_power_limit_mW_D" = "10500" register "stt_min_limit_D" = "10500" register "stt_m1_D" = "0x152" @@ -83,7 +79,6 @@ register "fast_ppt_limit_mW_E" = "24000" register "slow_ppt_limit_mW_E" = "20000" register "slow_ppt_time_constant_s_E" = "5" - register "sustained_power_limit_mW_E" = "12000" register "stt_min_limit_E" = "12000" register "stt_m1_E" = "0x18F" @@ -96,7 +91,6 @@ register "fast_ppt_limit_mW_F" = "12000" register "slow_ppt_limit_mW_F" = "12000" register "slow_ppt_time_constant_s_F" = "5" - register "sustained_power_limit_mW_F" = "8000" register "stt_min_limit_F" = "8000" register "stt_m1_F" = "0x18F" diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 858bcbe..dc147f8 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -73,13 +73,11 @@ uint32_t vrm_soc_current_limit_throttle_mA; /* tablet mode.*/ - uint32_t sustained_power_limit_mW_tablet; /* Thermal profile B*/ uint32_t fast_ppt_limit_mW_B; uint32_t slow_ppt_limit_mW_B; uint32_t slow_ppt_time_constant_s_B; - uint32_t sustained_power_limit_mW_B; uint16_t stt_min_limit_B; uint16_t stt_m1_B; uint16_t stt_m2_B; @@ -90,7 +88,6 @@ uint32_t fast_ppt_limit_mW_C; uint32_t slow_ppt_limit_mW_C; uint32_t slow_ppt_time_constant_s_C; - uint32_t sustained_power_limit_mW_C; uint16_t stt_min_limit_C; uint16_t stt_m1_C; uint16_t stt_m2_C; @@ -101,7 +98,6 @@ uint32_t fast_ppt_limit_mW_D; uint32_t slow_ppt_limit_mW_D; uint32_t slow_ppt_time_constant_s_D; - uint32_t sustained_power_limit_mW_D; uint16_t stt_min_limit_D; uint16_t stt_m1_D; uint16_t stt_m2_D; @@ -112,7 +108,6 @@ uint32_t fast_ppt_limit_mW_E; uint32_t slow_ppt_limit_mW_E; uint32_t slow_ppt_time_constant_s_E; - uint32_t sustained_power_limit_mW_E; uint16_t stt_min_limit_E; uint16_t stt_m1_E; uint16_t stt_m2_E; @@ -124,7 +119,6 @@ uint32_t fast_ppt_limit_mW_F; uint32_t slow_ppt_limit_mW_F; uint32_t slow_ppt_time_constant_s_F; - uint32_t sustained_power_limit_mW_F; uint16_t stt_min_limit_F; uint16_t stt_m1_F; uint16_t stt_m2_F; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 69f470b..dce9498 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -17,7 +17,7 @@ #include <stdint.h> #include "chip.h" -#define DPTC_TOTAL_UPDATE_PARAMS 14 +#define DPTC_TOTAL_UPDATE_PARAMS 13 struct dptc_input { uint16_t size; @@ -25,8 +25,8 @@ } __packed; -#define DPTC_INPUTS(_thermctllmit, _sustained, _spptTimeConst, _fast, _slow, \ - _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ +#define DPTC_INPUTS(_thermctllmit, _spptTimeConst, _fast, _slow, \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttAlphaApu, _sttSkinTempLimitApu) \ { \ .size = sizeof(struct dptc_input), \ @@ -36,10 +36,6 @@ .value = _thermctllmit, \ }, \ { \ - .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ - .value = _sustained, \ - }, \ - { \ .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ .value = _spptTimeConst, \ }, \ @@ -226,7 +222,6 @@ /* Normal mode DPTC values. */ struct dptc_input default_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW, config->slow_ppt_time_constant_s, config->fast_ppt_limit_mW, config->slow_ppt_limit_mW, @@ -244,7 +239,6 @@ /* Low/No Battery */ struct dptc_input no_battery_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW, config->slow_ppt_time_constant_s, config->fast_ppt_limit_mW, config->slow_ppt_limit_mW, @@ -263,7 +257,6 @@ #if (CONFIG(FEATURE_TABLET_MODE_DPTC)) struct dptc_input tablet_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_tablet, config->slow_ppt_time_constant_s, config->fast_ppt_limit_mW, config->slow_ppt_limit_mW, @@ -283,7 +276,6 @@ /* Profile B */ struct dptc_input thermal_B_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_B, config->slow_ppt_time_constant_s_B, config->fast_ppt_limit_mW_B, config->slow_ppt_limit_mW_B, @@ -302,7 +294,6 @@ /* Profile C */ struct dptc_input thermal_C_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_C, config->slow_ppt_time_constant_s_C, config->fast_ppt_limit_mW_C, config->slow_ppt_limit_mW_C, @@ -321,7 +312,6 @@ /* Profile D */ struct dptc_input thermal_D_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_D, config->slow_ppt_time_constant_s_D, config->fast_ppt_limit_mW_D, config->slow_ppt_limit_mW_D, @@ -340,7 +330,6 @@ /* Profile E */ struct dptc_input thermal_E_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_E, config->slow_ppt_time_constant_s_E, config->fast_ppt_limit_mW_E, config->slow_ppt_limit_mW_E, @@ -359,7 +348,6 @@ /* Profile F */ struct dptc_input thermal_F_input = DPTC_INPUTS( config->thermctl_limit_degreeC, - config->sustained_power_limit_mW_F, config->slow_ppt_time_constant_s_F, config->fast_ppt_limit_mW_F, config->slow_ppt_limit_mW_F, -- To view, visit https://review.coreboot.org/c/coreboot/+/73124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Gerrit-Change-Number: 73124 Gerrit-PatchSet: 7 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: xeon/spr: Set ACPI CPU string for 12bit
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73368 ) Change subject: xeon/spr: Set ACPI CPU string for 12bit ...................................................................... xeon/spr: Set ACPI CPU string for 12bit On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 899f5ae..7aa1fec 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -22,6 +22,10 @@ int default 255 +config ACPI_CPU_STRING + string + default "\\_SB.C%03X" + config MAX_SOCKET_UPD int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Gerrit-Change-Number: 73368 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/system76/adl-p: Add Oryx Pro 10 as a variant
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69210 ) Change subject: mb/system76/adl-p: Add Oryx Pro 10 as a variant ...................................................................... mb/system76/adl-p: Add Oryx Pro 10 as a variant oryp10 is nearly identical to the oryp9, with the differences being: - Uses DDR5 RAM instead of DDR4 RAM - Uses Realtek ALC1306 instead of TI TAS5825M - Has an option for OLED display Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp10.md M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/adl/Kconfig.name A src/mainboard/system76/adl/variants/oryp10/board_info.txt A src/mainboard/system76/adl/variants/oryp10/data.vbt A src/mainboard/system76/adl/variants/oryp10/gpio.c A src/mainboard/system76/adl/variants/oryp10/gpio_early.c A src/mainboard/system76/adl/variants/oryp10/hda_verb.c A src/mainboard/system76/adl/variants/oryp10/overridetree.cb A src/mainboard/system76/adl/variants/oryp10/romstage.c 11 files changed, 746 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0c51fe3..9a2660a 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -217,6 +217,7 @@ - [Oryx Pro 7](system76/oryp7.md) - [Oryx Pro 8](system76/oryp8.md) - [Oryx Pro 9](system76/oryp9.md) +- [Oryx Pro 10](system76/oryp10.md) ## Texas Instruments diff --git a/Documentation/mainboard/system76/oryp10.md b/Documentation/mainboard/system76/oryp10.md new file mode 100644 index 0000000..921585c --- /dev/null +++ b/Documentation/mainboard/system76/oryp10.md @@ -0,0 +1,69 @@ +# System76 Oryx Pro 10 (oryp10) + +## Specs + +- CPU + - Intel Core i7-12700H +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options: + - NVIDIA GeForce RTX 3070 Ti (Max-Q) + - NVIDIA GeForce RTX 3080 Ti (Max-Q) + - eDP options: + - 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0) + - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5) + - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1) + - 1x HDMI 2.1 + - 1x Mini DisplayPort 1.4 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz +- Networking + - Gigabit Ethernet + - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201) +- Power + - 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26) + - 80Wh 6-cell Lithium-ion battery +- Sound + - Realtek ALC1220 codec + - Realtek ALC1306 smart amp + - Internal speakers and microphone + - Combined 3.5mm headphone & microphone jack + - Combined 3.5mm microphone & S/PDIF jack + - HDMI, mDP, USB-C DP audio +- Storage + - 2x M.2 PCIe NVMe Gen 4 SSD + - MicroSD card reader (RTS5227S) +- USB + - 1x USB Type-C with Thunderbolt 4 + - 1x USB 3.2 (Gen 2) Type-C + - 2x USB 3.2 (Gen 1) Type-A +- Dimensions + - 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg + - 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg + + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | Macronix | ++---------------------+---------------------+ +| Model | MX25L25673G | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The flash chip (U61) is left of the DIMM slots. diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 00f19fb..83176d1 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 +if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -8,8 +8,8 @@ select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9 select EC_SYSTEM76_EC - select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 - select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 + select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE @@ -34,6 +34,7 @@ default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 + default "oryp10" if BOARD_SYSTEM76_ORYP10 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -43,18 +44,20 @@ default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 + default "oryp10" if BOARD_SYSTEM76_ORYP10 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 default "Galago Pro" if BOARD_SYSTEM76_GALP6 default "Lemur Pro" if BOARD_SYSTEM76_LEMP11 - default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 + default "oryp10" if BOARD_SYSTEM76_ORYP10 config CBFS_SIZE default 0xA00000 diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name index f36b752..ee7b6ff 100644 --- a/src/mainboard/system76/adl/Kconfig.name +++ b/src/mainboard/system76/adl/Kconfig.name @@ -9,3 +9,6 @@ config BOARD_SYSTEM76_ORYP9 bool "oryp9" + +config BOARD_SYSTEM76_ORYP10 + bool "oryp10" diff --git a/src/mainboard/system76/adl/variants/oryp10/board_info.txt b/src/mainboard/system76/adl/variants/oryp10/board_info.txt new file mode 100644 index 0000000..2a167f5 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp10 +Release year: 2022 diff --git a/src/mainboard/system76/adl/variants/oryp10/data.vbt b/src/mainboard/system76/adl/variants/oryp10/data.vbt new file mode 100644 index 0000000..df8bd14 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio.c b/src/mainboard/system76/adl/variants/oryp10/gpio.c new file mode 100644 index 0000000..5c56f80 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + _PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851 + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3 + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A11, NONE), // GPU_PROCHOT# + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + _PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_NC(GPP_A17, NONE), + _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD + PAD_NC(GPP_A19, NONE), + _PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N + PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_CPU) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone) + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851) + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851) + // GPP_B9 missing + // GPP_B10 missing + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_NC(GPP_B14, NONE), // Top swap override + PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap + // GPP_B19 missing + // GPP_B20 missing + // GPP_B21 missing + // GPP_B22 missing + PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2 + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA + // GPP_C8 missing + // GPP_C9 missing + // GPP_C10 missing + // GPP_C11 missing + // GPP_C12 missing + // GPP_C13 missing + // GPP_C14 missing + // GPP_C15 missing + // GPP_C16 missing + // GPP_C17 missing + // GPP_C18 missing + // GPP_C19 missing + // GPP_C20 missing + // GPP_C21 missing + // GPP_C22 missing + // GPP_C23 missing + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN + // GPP_D5 (SSD0_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST# + // GPP_D7 (WLAN_CLKREQ#) configured by FSP + // GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED# + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4 + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5 + // GPP_E18 (TBTA_LSX2_TXD) configured by FSP + // GPP_E19 (TBTA_LSX2_RXD) configured by FSP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), // Strap + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + // GPP_F5 (CNVI_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap + // GPP_F8 missing + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap + PAD_NC(GPP_F11, NONE), + PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6 + PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7 + PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC + PAD_NC(GPP_F18, NONE), + // GPP_F19 (CARD_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2# + PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad) + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad) + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer) + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer) + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RX) configured in bootblock + // GPP_H11 (UART0_TX) configured in bootblock + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + // GPP_H14 missing + PAD_NC(GPP_H15, NONE), + // GPP_H16 missing + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + // GPP_H19 (SSD1_CLKREQ#) configured by FSP + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + // GPP_H23 (GLAN_CLKREQ#) configured by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE# + PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK + PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp10/gpio_early.c b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c new file mode 100644 index 0000000..382fe0f --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c new file mode 100644 index 0000000..3e1ec90 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155867f5, /* Subsystem ID */ + 152, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155867f5), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), + + // Enable DMIC microphone on ALC1220 + 0x02050036, 0x02042a6a, 0x02050008, 0x0204800b, + + // ALC1306 smart amp + 0x02050027, 0x02040010, 0x02050029, 0x02040000, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003f, + 0x0205002b, 0x02041000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040004, + 0x0205002b, 0x02040600, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x02040006, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x0204c0c0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204ffd0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040080, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040880, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003a, + 0x0205002b, 0x02040dfe, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x02040442, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040005, + 0x0205002b, 0x02040880, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040006, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040008, + 0x0205002b, 0x0204b000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204002e, + 0x0205002b, 0x02040800, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x020400c3, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x0204d4a0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x020400cc, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x0204400a, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x020400c1, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x02040320, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040039, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003b, + 0x0205002b, 0x0204ffff, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x02049142, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x02040006, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x020400c0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fcf0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040080, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040880, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040880, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003c, + 0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x02040006, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040080, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040062, + 0x0205002b, 0x02048000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040063, + 0x0205002b, 0x02045f5f, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040064, + 0x0205002b, 0x02042000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040065, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040066, + 0x0205002b, 0x02044004, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040067, + 0x0205002b, 0x02040802, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040068, + 0x0205002b, 0x0204890f, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040069, + 0x0205002b, 0x0204e021, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040070, + 0x0205002b, 0x02048012, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040071, + 0x0205002b, 0x02043450, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040072, + 0x0205002b, 0x02040123, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040073, + 0x0205002b, 0x02044543, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040074, + 0x0205002b, 0x02042100, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040075, + 0x0205002b, 0x02044321, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040076, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040046, + 0x0205002b, 0x0204c22e, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040050, + 0x0205002b, 0x02048200, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040051, + 0x0205002b, 0x02040707, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040052, + 0x0205002b, 0x02044090, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x02040090, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x0204721f, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040012, + 0x0205002b, 0x0204dfdf, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204009e, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040004, + 0x0205002b, 0x02040500, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006a, + 0x0205002b, 0x02040006, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204006c, + 0x0205002b, 0x02040000, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x02040060, + 0x0205002b, 0x02042213, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003a, + 0x0205002b, 0x02041dfe, 0x0205002c, 0x0204b424, + 0x02050027, 0x02040010, 0x02050029, 0x0204003f, + 0x0205002b, 0x02043000, 0x0205002c, 0x0204b424, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb new file mode 100644 index 0000000..ddf5876 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -0,0 +1,201 @@ +chip soc/intel/alderlake + # HACK: Limit PL4 to prevent power off on battery power. + register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 115, + .tdp_psyspl2 = 135, + .tdp_pl4 = 72, + }" + + # Thermal + register "tcc_offset" = "10" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x65f5 inherit + + device ref pcie5_0 on + # CPU PCIe RP#2 x8, Clock 3 (DGPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR, + }" + end + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD" + end + device ref pcie4_0 on + # CPU PCIe RP#1 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + end + device ref pcie4_1 on + # CPU PCIe RP#3 x4, Clock 4 (SSD2) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR, + }" + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Per-KB"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + end + end + end + device ref sata off end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp6 on + # PCIe RP#6 x1, Clock 6 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable connected directly to 3.3VS? + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "6" # CARD_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe RP#8 x1, Clock 5 (GLAN) + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # XXX: Enable connected directly to VDD3? + #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "5" # GLAN_CLKREQ# + device generic 0 on end + end + end + + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TYPEC2 + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c new file mode 100644 index 0000000..48714e0 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .rcomp = { .resistor = 100, }, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Gerrit-Change-Number: 69210 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XL] Change in coreboot[master]: mb/system76/adl: Add Oryx Pro 9 as a variant
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65610 ) Change subject: mb/system76/adl: Add Oryx Pro 9 as a variant ...................................................................... mb/system76/adl: Add Oryx Pro 9 as a variant The Oryx Pro 9 (oryp9) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - Both M.2 NVME SSD slots (with MZVL2500HCJQ) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - Discrete/Hybrid graphics - HDMI output (requires NVIDIA GPU) - Mini DisplayPort output (requires NVIDIA GPU) - Detection of devices in TBT slot on boot Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65610 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp9.md M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/adl/Kconfig.name M src/mainboard/system76/adl/Makefile.inc A src/mainboard/system76/adl/variants/oryp9/board_info.txt A src/mainboard/system76/adl/variants/oryp9/data.vbt A src/mainboard/system76/adl/variants/oryp9/gpio.c A src/mainboard/system76/adl/variants/oryp9/gpio_early.c A src/mainboard/system76/adl/variants/oryp9/hda_verb.c A src/mainboard/system76/adl/variants/oryp9/overridetree.cb A src/mainboard/system76/adl/variants/oryp9/romstage.c A src/mainboard/system76/adl/variants/oryp9/tas5825m.c 13 files changed, 1,856 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 342a1f1..0c51fe3 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -216,6 +216,7 @@ - [Oryx Pro 6](system76/oryp6.md) - [Oryx Pro 7](system76/oryp7.md) - [Oryx Pro 8](system76/oryp8.md) +- [Oryx Pro 9](system76/oryp9.md) ## Texas Instruments diff --git a/Documentation/mainboard/system76/oryp9.md b/Documentation/mainboard/system76/oryp9.md new file mode 100644 index 0000000..87e176b --- /dev/null +++ b/Documentation/mainboard/system76/oryp9.md @@ -0,0 +1,67 @@ +# System76 Oryx Pro 9 (oryp9) + +## Specs + +- CPU + - Intel Core i7-12700H +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - dGPU options: + - NVIDIA GeForce RTX 3070 Ti (Max-Q) + - NVIDIA GeForce RTX 3080 Ti (Max-Q) + - eDP options: + - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5) + - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1) + - 1x HDMI 2.1 + - 1x Mini DisplayPort 1.4 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz +- Networking + - Gigabit Ethernet + - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201) +- Power + - 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26) + - 80Wh 6-cell Lithium-ion battery +- Sound + - Realtek ALC1220 codec + - TI TAS5825M smart amp + - Internal speakers and microphone + - Combined 3.5mm headphone & microphone jack + - Combined 3.5mm microphone & S/PDIF jack + - HDMI, mDP, USB-C DP audio +- Storage + - 2x M.2 PCIe NVMe Gen 4 SSD + - MicroSD card reader (RTS5227S) +- USB + - 1x USB Type-C with Thunderbolt 4 + - 1x USB 3.2 (Gen 2) Type-C + - 2x USB 3.2 (Gen 1) Type-A +- Dimensions + - 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg + - 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | Macronix | ++---------------------+---------------------+ +| Model | MX25L25673G | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The flash chip (U61) is left of the DIMM slots. diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 9329ee0..00f19fb 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 +if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -6,8 +6,10 @@ select DRIVERS_I2C_HID select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9 select EC_SYSTEM76_EC - select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 + select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 + select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE @@ -31,6 +33,7 @@ default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 + default "oryp9" if BOARD_SYSTEM76_ORYP9 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -39,16 +42,19 @@ default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 + default "oryp9" if BOARD_SYSTEM76_ORYP9 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 default "Galago Pro" if BOARD_SYSTEM76_GALP6 default "Lemur Pro" if BOARD_SYSTEM76_LEMP11 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 default "lemp11" if BOARD_SYSTEM76_LEMP11 + default "oryp9" if BOARD_SYSTEM76_ORYP9 config CBFS_SIZE default 0xA00000 @@ -59,6 +65,9 @@ config DIMM_SPD_SIZE default 512 +config ONBOARD_VGA_IS_PRIMARY + default y + config POST_DEVICE default n diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name index fa0b28b..f36b752 100644 --- a/src/mainboard/system76/adl/Kconfig.name +++ b/src/mainboard/system76/adl/Kconfig.name @@ -6,3 +6,6 @@ config BOARD_SYSTEM76_LEMP11 bool "lemp11" + +config BOARD_SYSTEM76_ORYP9 + bool "oryp9" diff --git a/src/mainboard/system76/adl/Makefile.inc b/src/mainboard/system76/adl/Makefile.inc index f3dc7e1..9dea9f3 100644 --- a/src/mainboard/system76/adl/Makefile.inc +++ b/src/mainboard/system76/adl/Makefile.inc @@ -8,5 +8,6 @@ ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c SPD_SOURCES = samsung-P4AAF165WA-BCWDE diff --git a/src/mainboard/system76/adl/variants/oryp9/board_info.txt b/src/mainboard/system76/adl/variants/oryp9/board_info.txt new file mode 100644 index 0000000..6308388 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp9 +Release year: 2022 diff --git a/src/mainboard/system76/adl/variants/oryp9/data.vbt b/src/mainboard/system76/adl/variants/oryp9/data.vbt new file mode 100644 index 0000000..0807054 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl/variants/oryp9/gpio.c b/src/mainboard/system76/adl/variants/oryp9/gpio.c new file mode 100644 index 0000000..5c56f80 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + _PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851 + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3 + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A11, NONE), // GPU_PROCHOT# + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + _PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_NC(GPP_A17, NONE), + _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD + PAD_NC(GPP_A19, NONE), + _PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N + PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_CPU) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone) + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851) + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851) + // GPP_B9 missing + // GPP_B10 missing + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_NC(GPP_B14, NONE), // Top swap override + PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap + // GPP_B19 missing + // GPP_B20 missing + // GPP_B21 missing + // GPP_B22 missing + PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2 + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA + // GPP_C8 missing + // GPP_C9 missing + // GPP_C10 missing + // GPP_C11 missing + // GPP_C12 missing + // GPP_C13 missing + // GPP_C14 missing + // GPP_C15 missing + // GPP_C16 missing + // GPP_C17 missing + // GPP_C18 missing + // GPP_C19 missing + // GPP_C20 missing + // GPP_C21 missing + // GPP_C22 missing + // GPP_C23 missing + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN + // GPP_D5 (SSD0_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST# + // GPP_D7 (WLAN_CLKREQ#) configured by FSP + // GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED# + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4 + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5 + // GPP_E18 (TBTA_LSX2_TXD) configured by FSP + // GPP_E19 (TBTA_LSX2_RXD) configured by FSP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), // Strap + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + // GPP_F5 (CNVI_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap + // GPP_F8 missing + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap + PAD_NC(GPP_F11, NONE), + PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6 + PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7 + PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC + PAD_NC(GPP_F18, NONE), + // GPP_F19 (CARD_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2# + PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad) + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad) + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer) + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer) + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RX) configured in bootblock + // GPP_H11 (UART0_TX) configured in bootblock + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + // GPP_H14 missing + PAD_NC(GPP_H15, NONE), + // GPP_H16 missing + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + // GPP_H19 (SSD1_CLKREQ#) configured by FSP + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + // GPP_H23 (GLAN_CLKREQ#) configured by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE# + PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK + PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp9/gpio_early.c b/src/mainboard/system76/adl/variants/oryp9/gpio_early.c new file mode 100644 index 0000000..382fe0f --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp9/hda_verb.c b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c new file mode 100644 index 0000000..31d93a9 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155867f5, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155867f5), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb new file mode 100644 index 0000000..a58c4c3 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -0,0 +1,188 @@ +chip soc/intel/alderlake + # HACK: Limit PL4 to prevent power off on battery power. + register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 115, + .tdp_psyspl2 = 135, + .tdp_pl4 = 72, + }" + + # Thermal + register "tcc_offset" = "10" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x65f5 inherit + + device ref pcie5_0 on + # CPU PCIe RP#2 x8, Clock 3 (DGPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR, + }" + end + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD" + end + device ref pcie4_0 on + # CPU PCIe RP#1 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + end + device ref pcie4_1 on + # CPU PCIe RP#3 x4, Clock 4 (SSD2) + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR, + }" + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Per-KB"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + end + end + end + device ref sata off end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 on + # PCIe RP#6 x1, Clock 6 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp8 on + # PCIe RP#8 x1, Clock 5 (GLAN) + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TYPEC2 + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref smbus on + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + end + end +end diff --git a/src/mainboard/system76/adl/variants/oryp9/romstage.c b/src/mainboard/system76/adl/variants/oryp9/romstage.c new file mode 100644 index 0000000..d16b4f8 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/adl/variants/oryp9/tas5825m.c b/src/mainboard/system76/adl/variants/oryp9/tas5825m.c new file mode 100644 index 0000000..15449cd --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/tas5825m.c @@ -0,0 +1,1238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/i2c/tas5825m/tas5825m.h> + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0xFE, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x2D, 0x6A, 0x86, + 0x00, 0x2D, 0x6A, 0x86, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xDE, 0x71, 0xB1, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x02, 0x81, 0xE8, 0x8F, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF5, 0xD6, 0xD3, 0xF0, 0x63, 0x93, 0xB0, + 0x07, 0xA7, 0x5A, 0xBD, 0x0F, 0x9C, 0x6C, 0x50, + 0xF8, 0x62, 0xCE, 0x70, 0x07, 0xF4, 0x31, 0x72, + 0xF0, 0x73, 0x27, 0x53, 0x07, 0x98, 0xFE, 0x8B, + 0x0F, 0x8C, 0xD8, 0xAD, 0xF8, 0x72, 0xD0, 0x02, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE3, 0xCF, 0xE3, 0xF0, 0x38, 0x60, 0x3B, + 0x07, 0xE3, 0xCF, 0xE3, 0x0F, 0xC7, 0x6A, 0x36, + 0xF8, 0x38, 0x2A, 0xAB, 0x07, 0xEB, 0x43, 0x17, + 0xF0, 0x29, 0x79, 0xD3, 0x07, 0xEB, 0x43, 0x17, + 0x0F, 0xD6, 0x50, 0x6B, 0xF8, 0x29, 0x44, 0x10, + 0x07, 0xF0, 0xED, 0x8D, 0xF0, 0x42, 0x66, 0x35, + 0x07, 0xCD, 0xBB, 0x6F, 0x0F, 0xBD, 0x99, 0xCB, + 0xF8, 0x41, 0x57, 0x04, 0x08, 0x19, 0xA4, 0x18, + 0xF0, 0x0F, 0xF2, 0xD6, 0x07, 0xD7, 0x7B, 0xA8, + 0x0F, 0xF0, 0x60, 0x5B, 0xF8, 0x0F, 0x33, 0x70, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xCF, 0xE3, + 0xF0, 0x38, 0x60, 0x3B, 0x07, 0xE3, 0xCF, 0xE3, + 0x0F, 0xC7, 0x6A, 0x36, 0xF8, 0x38, 0x2A, 0xAB, + 0x07, 0xEB, 0x43, 0x17, 0xF0, 0x29, 0x79, 0xD3, + 0x07, 0xEB, 0x43, 0x17, 0x0F, 0xD6, 0x50, 0x6B, + 0xF8, 0x29, 0x44, 0x10, 0x07, 0xF0, 0xED, 0x8D, + 0xF0, 0x42, 0x66, 0x35, 0x07, 0xCD, 0xBB, 0x6F, + 0x0F, 0xBD, 0x99, 0xCB, 0xF8, 0x41, 0x57, 0x04, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x19, 0xA4, 0x18, 0xF0, 0x0F, 0xF2, 0xD6, + 0x07, 0xD7, 0x7B, 0xA8, 0x0F, 0xF0, 0x60, 0x5B, + 0xF8, 0x0F, 0x33, 0x70, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x87, 0x5E, 0xC2, 0xFF, 0x02, 0xC8, 0x72, + 0x00, 0x76, 0xEA, 0x00, 0x0F, 0xDB, 0x79, 0xE0, + 0xF8, 0x23, 0x74, 0xEC + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4E, 0xBB); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4F, 0xB0); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x0F); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x6B, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x6C, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/65610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Gerrit-Change-Number: 65610 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Allow channel 0 for memory-down
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65567 ) Change subject: soc/intel/alderlake: Allow channel 0 for memory-down ...................................................................... soc/intel/alderlake: Allow channel 0 for memory-down Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/soc/intel/alderlake/meminit.c 1 file changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jeremy Soller: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index cbc2b5c..862a322 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -54,8 +54,8 @@ * configuration. */ .half_channel = BIT(0), - /* In mixed topologies, channel 1 is always memory-down. */ - .mixed_topo = BIT(1), + /* In mixed topologies, either channel 0 or 1 can be memory-down. */ + .mixed_topo = BIT(0) | BIT(1), }, }, [MEM_TYPE_DDR5] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/65567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Gerrit-Change-Number: 65567 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/system76/adl: Add Lemur Pro 11 as a variant
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65384 ) Change subject: mb/system76/adl: Add Lemur Pro 11 as a variant ...................................................................... mb/system76/adl: Add Lemur Pro 11 as a variant The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65384 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/lemp11.md M src/mainboard/system76/adl/Kconfig M src/mainboard/system76/adl/Kconfig.name M src/mainboard/system76/adl/Makefile.inc A src/mainboard/system76/adl/spd/samsung-P4AAF165WA-BCWDE.spd.hex A src/mainboard/system76/adl/variants/lemp11/board_info.txt A src/mainboard/system76/adl/variants/lemp11/data.vbt A src/mainboard/system76/adl/variants/lemp11/gpio.c A src/mainboard/system76/adl/variants/lemp11/gpio_early.c A src/mainboard/system76/adl/variants/lemp11/hda_verb.c A src/mainboard/system76/adl/variants/lemp11/overridetree.cb A src/mainboard/system76/adl/variants/lemp11/romstage.c 13 files changed, 601 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a1cd9f5..342a1f1 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -211,6 +211,7 @@ - [Gazelle 16](system76/gaze16.md) - [Lemur Pro 9](system76/lemp9.md) - [Lemur Pro 10](system76/lemp10.md) +- [Lemur Pro 11](system76/lemp11.md) - [Oryx Pro 5](system76/oryp5.md) - [Oryx Pro 6](system76/oryp6.md) - [Oryx Pro 7](system76/oryp7.md) diff --git a/Documentation/mainboard/system76/lemp11.md b/Documentation/mainboard/system76/lemp11.md new file mode 100644 index 0000000..f05d63a --- /dev/null +++ b/Documentation/mainboard/system76/lemp11.md @@ -0,0 +1,62 @@ +# System76 Lemur Pro 11 (lemp11) + +## Specs + +- CPU + - Intel Core i5-1235U + - Intel Core i7-1255U +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - Intel Iris Xe Graphics + - eDP 14.0" 1920x1080@60Hz LCD + - 1x HDMI 2.1 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE) + - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz +- Networking + - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201) +- Power + - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012) + - USB-C charging, compatible with 65W+ chargers + - 73Wh 4-cell Lithium-ion battery (L140BAT-4) +- Sound + - Realtek ALC256 codec + - Internal speakers and microphone + - Combined 3.5 mm headphone/microphone jack + - HDMI, USB-C DisplayPort audio +- Storage + - M.2 PCIe NVMe Gen 4 SSD + - M.2 PCIe NVMe Gen 3 or SATA 3 SSD + - MicroSD card reader (RTS5227S) +- USB + - 1x USB Type-C with Thunderbolt 4 + - 1x USB 3.2 (Gen 2) Type-A + - 1x USB 3.2 (Gen 1) Type-A +- Dimensions + - 1.65cm x 32.2cm x 21.68cm, 1.15kg + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | Macronix | ++---------------------+---------------------+ +| Model | MX25L25673G | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The flash chip (U41) is left of the DIMM slot. diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index a450534..9329ee0 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 +if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,6 +11,7 @@ select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11 select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_TPM2 @@ -29,6 +30,7 @@ config VARIANT_DIR default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "lemp11" if BOARD_SYSTEM76_LEMP11 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -36,14 +38,17 @@ config MAINBOARD_PART_NUMBER default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "lemp11" if BOARD_SYSTEM76_LEMP11 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 default "Galago Pro" if BOARD_SYSTEM76_GALP6 + default "Lemur Pro" if BOARD_SYSTEM76_LEMP11 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 default "galp6" if BOARD_SYSTEM76_GALP6 + default "lemp11" if BOARD_SYSTEM76_LEMP11 config CBFS_SIZE default 0xA00000 diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name index 5e3aee3..fa0b28b 100644 --- a/src/mainboard/system76/adl/Kconfig.name +++ b/src/mainboard/system76/adl/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_SYSTEM76_GALP6 bool "galp6" + +config BOARD_SYSTEM76_LEMP11 + bool "lemp11" diff --git a/src/mainboard/system76/adl/Makefile.inc b/src/mainboard/system76/adl/Makefile.inc index 8989d5c..f3dc7e1 100644 --- a/src/mainboard/system76/adl/Makefile.inc +++ b/src/mainboard/system76/adl/Makefile.inc @@ -8,3 +8,5 @@ ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c + +SPD_SOURCES = samsung-P4AAF165WA-BCWDE diff --git a/src/mainboard/system76/adl/spd/samsung-P4AAF165WA-BCWDE.spd.hex b/src/mainboard/system76/adl/spd/samsung-P4AAF165WA-BCWDE.spd.hex new file mode 100644 index 0000000..28e4a61 --- /dev/null +++ b/src/mainboard/system76/adl/spd/samsung-P4AAF165WA-BCWDE.spd.hex @@ -0,0 +1,33 @@ +# Samsung P4AAF165WA-BCWDE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 DE DE +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 50 34 41 41 46 31 36 +35 57 41 2D 42 43 57 44 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/system76/adl/variants/lemp11/board_info.txt b/src/mainboard/system76/adl/variants/lemp11/board_info.txt new file mode 100644 index 0000000..301c2d3 --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/board_info.txt @@ -0,0 +1,2 @@ +Board name: lemp11 +Release year: 2022 diff --git a/src/mainboard/system76/adl/variants/lemp11/data.vbt b/src/mainboard/system76/adl/variants/lemp11/data.vbt new file mode 100644 index 0000000..3d822c3 --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl/variants/lemp11/gpio.c b/src/mainboard/system76/adl/variants/lemp11/gpio.c new file mode 100644 index 0000000..e8eb1e2 --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE# + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT# + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + // GPP_B9 missing + // GPP_B10 missing + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST# + PAD_NC(GPP_B18, NONE), // NO REBOOT strap + // GPP_B19 missing + // GPP_B20 missing + // GPP_B21 missing + // GPP_B22 missing + PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA + // GPP_C8 missing + // GPP_C9 missing + // GPP_C10 missing + // GPP_C11 missing + // GPP_C12 missing + // GPP_C13 missing + // GPP_C14 missing + // GPP_C15 missing + // GPP_C16 missing + // GPP_C17 missing + // GPP_C18 missing + // GPP_C19 missing + // GPP_C20 missing + // GPP_C21 missing + // GPP_C22 missing + // GPP_C23 missing + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + // GPP_D5 (SSD0_CLKREQ#) configured by FSP + // GPP_D6 (SSD1_CLKREQ#) configured by FSP + // GPP_D7 (WLAN_CLKREQ#) configured by FSP + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED# + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + // GPP_E18 (TBT_LSX0_TXD) configured by FSP + // GPP_E19 (TBT_LSX0_RXD) configured by FSP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + // GPP_F5 (CNVI_CLKREQ) configured by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap + // GPP_F8 missing + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST# + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + // GPP_F19 (CARD_CLKREQ#) configured by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST# + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD + // GPP_H10 (UART0_RX) configured in bootblock + // GPP_H11 (UART0_TX) configured in bootblock + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1 + PAD_NC(GPP_H13, NONE), + // GPP_H14 missing + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK + // GPP_H16 missing + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), // DMIC_CLK + PAD_NC(GPP_R7, NONE), // DMIC_DAT + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/lemp11/gpio_early.c b/src/mainboard/system76/adl/variants/lemp11/gpio_early.c new file mode 100644 index 0000000..c80c798 --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/lemp11/hda_verb.c b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c new file mode 100644 index 0000000..d03c67a --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, + 0x15587718, + 11, + AZALIA_SUBVENDOR(0, 0x15587718), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb new file mode 100644 index 0000000..82943cb --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -0,0 +1,161 @@ +chip soc/intel/alderlake + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 46, + .tdp_pl4 = 65, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x7718 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# + register "srcclk_pin" = "0" # SSD0_CLKREQ# + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 3G/LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp6 on + # PCIe RP#6 x1, Clock 6 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp9 on + # PCIe RP#9 x4, Clock 1 (SSD1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST# + register "srcclk_pin" = "1" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC1 + use usb2_port3 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/system76/adl/variants/lemp11/romstage.c b/src/mainboard/system76/adl/variants/lemp11/romstage.c new file mode 100644 index 0000000..989b5df --- /dev/null +++ b/src/mainboard/system76/adl/variants/lemp11/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MIXED, + .cbfs_index = 0, + .smbus[1] = { .addr_dimm[0] = 0x52, }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/65384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Gerrit-Change-Number: 65384 Gerrit-PatchSet: 25 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dt
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73174 ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dt ...................................................................... mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dt BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 2c13c64..ded70f2 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -36,6 +36,17 @@ .tx_downscale_amp = 0x00, }" # Type-A port A2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(6) | \ + USB_PORT_WAKE_ENABLE(7) | \ + USB_PORT_WAKE_ENABLE(8)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4)" + register "tcc_offset" = "0" # TCC of 100C register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 55, -- To view, visit https://review.coreboot.org/c/coreboot/+/73174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Gerrit-Change-Number: 73174 Gerrit-PatchSet: 13 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/intel/alderlake: Add UWES ASL into xhci.asl
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73173 ) Change subject: soc/intel/alderlake: Add UWES ASL into xhci.asl ...................................................................... soc/intel/alderlake: Add UWES ASL into xhci.asl Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao(a)wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/acpi/xhci.asl M src/soc/intel/alderlake/include/soc/usb.h 2 files changed, 106 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index 3ccc22e..465f0aa 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -2,6 +2,65 @@ #include <soc/gpe.h> +#define PORTSCN_OFFSET 0x480 +#define PORTSCXUSB3_OFFSET 0x540 + +#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 +/* + * And port status/control reg with RO and RWS bits + * RO bits: 0, 2:3, 10:13, 24, 28:30 + * RWS bits: 5:9, 14:16, 25:27 + */ +#define RO_BITS_OFF_MASK ~0x80FE0012 + +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + Local0 = Arg1 + ((Arg0 - 1) * 0x10) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Local0 = PSCT + + Local0 &= RO_BITS_OFF_MASK + /* Set WCE and WDE bits */ + Local0 |= WAKE_ON_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Local0 = Arg0 + + While (1) { + FindSetRightBit (Local0, Local1) + If (Local1 == 0) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + */ + Local0 &= (Local0 - 1) + } +} + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -10,6 +69,20 @@ Name (_PRW, Package () { GPE0_PME_B0, 3 }) + OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + Field (XPRT, AnyAcc, NoLock, Preserve) + { + Offset (0x10), + , 16, + XMEM, 16, /* MEM_BASE */ + } + + Method (_DSW, 3) + { + UWES ((\U2WE & 0xFFF), PORTSCN_OFFSET, XMEM) + UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM) + } + Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 0eb6160..2a701c8 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -163,5 +163,11 @@ .ocpin = (pin), \ } +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/73173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Gerrit-Change-Number: 73173 Gerrit-PatchSet: 15 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: security/tpm: add TPM log format as per 2.0 spec
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68748 ) Change subject: security/tpm: add TPM log format as per 2.0 spec ...................................................................... security/tpm: add TPM log format as per 2.0 spec Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68748 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm2_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm2.c M src/security/tpm/tspi/logs.h 8 files changed, 429 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h b/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h index a45a212..144d55a 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h +++ b/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h @@ -9,6 +9,21 @@ #define TCPA_SPEC_ID_EVENT_SIGNATURE "Spec ID Event00" #define TCG_EFI_SPEC_ID_EVENT_SIGNATURE "Spec ID Event03" +#define TPM2_ALG_ERROR 0x0000 +#define TPM2_ALG_HMAC 0x0005 +#define TPM2_ALG_NULL 0x0010 +#define TPM2_ALG_SHA1 0x0004 +#define TPM2_ALG_SHA256 0x000B +#define TPM2_ALG_SHA384 0x000C +#define TPM2_ALG_SHA512 0x000D +#define TPM2_ALG_SM3_256 0x0012 + +#define SHA1_DIGEST_SIZE 20 +#define SHA256_DIGEST_SIZE 32 +#define SHA384_DIGEST_SIZE 48 +#define SHA512_DIGEST_SIZE 64 +#define SM3_256_DIGEST_SIZE 32 + #define EV_PREBOOT_CERT 0x00000000 #define EV_POST_CODE 0x00000001 #define EV_UNUSED 0x00000002 @@ -39,4 +54,26 @@ uint8_t vendor_info_size; } __packed; +struct tpm_digest_sizes { + uint16_t alg_id; + uint16_t digest_size; +} __packed; + +struct tcg_efi_spec_id_event { + uint32_t pcr_index; + uint32_t event_type; + uint8_t digest[20]; + uint32_t event_size; + uint8_t signature[16]; + uint32_t platform_class; + uint8_t spec_version_minor; + uint8_t spec_version_major; + uint8_t spec_errata; + uint8_t uintn_size; + uint32_t num_of_algorithms; + struct tpm_digest_sizes digest_sizes[0]; /* variable number of members */ + /* uint8_t vendor_info_size; */ + /* uint8_t vendor_info[vendor_info_size]; */ +} __packed; + #endif diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 467773d..8466d80 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -98,7 +98,7 @@ prompt "TPM event log format" depends on TPM_MEASURED_BOOT default TPM_LOG_TPM1 if TPM1 - default TPM_LOG_CB + default TPM_LOG_TPM2 if TPM2 config TPM_LOG_CB bool "coreboot's custom format" @@ -110,6 +110,29 @@ help Log per TPM 1.2 specification. See "TCG PC Client Specific Implementation Specification for Conventional BIOS". +config TPM_LOG_TPM2 + bool "TPM 2.0 format" + depends on TPM2 + help + Log per TPM 2.0 specification. + See "TCG PC Client Platform Firmware Profile Specification". + +endchoice + +choice + prompt "TPM2 hashing algorithm" + depends on TPM_MEASURED_BOOT && TPM_LOG_TPM2 + default TPM_HASH_SHA1 if TPM1 + default TPM_HASH_SHA256 if TPM2 + +config TPM_HASH_SHA1 + bool "SHA1" +config TPM_HASH_SHA256 + bool "SHA256" +config TPM_HASH_SHA384 + bool "SHA384" +config TPM_HASH_SHA512 + bool "SHA512" endchoice diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a8c25d6..ae06cb0 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -67,4 +67,10 @@ postcar-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c bootblock-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c +ramstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +romstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +verstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +postcar-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +bootblock-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c + endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tpm2_log_serialized.h b/src/security/tpm/tpm2_log_serialized.h new file mode 100644 index 0000000..2b4e43c --- /dev/null +++ b/src/security/tpm/tpm2_log_serialized.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __TPM2_LOG_SERIALIZED_H__ +#define __TPM2_LOG_SERIALIZED_H__ + +#include <commonlib/bsd/tpm_log_defs.h> + +#define TPM_20_SPEC_ID_EVENT_SIGNATURE "Spec ID Event03" +#define TPM_20_LOG_DATA_MAX_LENGTH 50 + +#define TPM_20_LOG_VI_MAGIC 0x32544243 /* "CBT2" in LE */ +#define TPM_20_LOG_VI_MAJOR 1 +#define TPM_20_LOG_VI_MINOR 0 + +/* + * TPM2.0 log entries can't be generally represented as C structures due to + * varying number of digests and their sizes. However, it works as long as + * we're only using single kind of digests. + */ +#if CONFIG(TPM_LOG_TPM2) +# if CONFIG(TPM_HASH_SHA1) +# define TPM_20_LOG_DIGEST_MAX_LENGTH SHA1_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA256) +# define TPM_20_LOG_DIGEST_MAX_LENGTH SHA256_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA384) +# define TPM_20_LOG_DIGEST_MAX_LENGTH SHA384_DIGEST_SIZE +# endif +# if CONFIG(TPM_HASH_SHA512) +# define TPM_20_LOG_DIGEST_MAX_LENGTH SHA512_DIGEST_SIZE +# endif + +# ifndef TPM_20_LOG_DIGEST_MAX_LENGTH +# error "Misconfiguration: failed to determine TPM hashing algorithm" +# endif +#else +# define TPM_20_LOG_DIGEST_MAX_LENGTH 1 /* To avoid compilation error */ +#endif + +/* TCG_PCR_EVENT2 */ +struct tpm_2_log_entry { + uint32_t pcr; + uint32_t event_type; + uint32_t digest_count; /* Always 1 in current implementation */ + uint16_t digest_type; + uint8_t digest[TPM_20_LOG_DIGEST_MAX_LENGTH]; + uint32_t data_length; + uint8_t data[TPM_20_LOG_DATA_MAX_LENGTH]; +} __packed; + +struct tpm_2_vendor { + uint8_t reserved; + uint8_t version_major; + uint8_t version_minor; + uint32_t magic; + uint16_t max_entries; + uint16_t num_entries; + uint32_t entry_size; +} __packed; + +struct tpm_2_log_table { + struct tcg_efi_spec_id_event header; /* TCG_PCR_EVENT actually */ + struct tpm_digest_sizes digest_sizes[1]; + uint8_t vendor_info_size; + struct tpm_2_vendor vendor; + struct tpm_2_log_entry entries[0]; /* Variable number of entries */ +} __packed; + +#endif diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 5de0aa2..33f363c 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -4,6 +4,7 @@ #define TSPI_H_ #include <security/tpm/tpm1_log_serialized.h> +#include <security/tpm/tpm2_log_serialized.h> #include <security/tpm/tspi/logs.h> #include <security/tpm/tss.h> #include <commonlib/tpm_log_serialized.h> @@ -32,6 +33,8 @@ return tpm_cb_log_cbmem_init(); if (CONFIG(TPM_LOG_TPM1)) return tpm1_log_cbmem_init(); + if (CONFIG(TPM_LOG_TPM2)) + return tpm2_log_cbmem_init(); return NULL; } @@ -45,6 +48,8 @@ tpm_cb_preram_log_clear(); else if (CONFIG(TPM_LOG_TPM1)) tpm1_preram_log_clear(); + else if (CONFIG(TPM_LOG_TPM2)) + tpm2_preram_log_clear(); } /** @@ -56,6 +61,8 @@ return tpm_cb_log_get_size(log_table); if (CONFIG(TPM_LOG_TPM1)) return tpm1_log_get_size(log_table); + if (CONFIG(TPM_LOG_TPM2)) + return tpm2_log_get_size(log_table); return 0; } @@ -68,6 +75,8 @@ tpm_cb_log_copy_entries(from, to); else if (CONFIG(TPM_LOG_TPM1)) tpm1_log_copy_entries(from, to); + else if (CONFIG(TPM_LOG_TPM2)) + tpm2_log_copy_entries(from, to); } /** @@ -80,6 +89,8 @@ return tpm_cb_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); if (CONFIG(TPM_LOG_TPM1)) return tpm1_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); + if (CONFIG(TPM_LOG_TPM2)) + return tpm2_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); return 1; } @@ -100,6 +111,8 @@ tpm_cb_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); else if (CONFIG(TPM_LOG_TPM1)) tpm1_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); + else if (CONFIG(TPM_LOG_TPM2)) + tpm2_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); } /** @@ -111,6 +124,8 @@ tpm_cb_log_dump(); else if (CONFIG(TPM_LOG_TPM1)) tpm1_log_dump(); + else if (CONFIG(TPM_LOG_TPM2)) + tpm2_log_dump(); } /** diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 2416077..ffa4867 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -22,6 +22,19 @@ # define TPM_MEASURE_ALGO VB2_HASH_SHA256 #elif CONFIG(TPM_LOG_TPM1) # define TPM_MEASURE_ALGO VB2_HASH_SHA1 +#elif CONFIG(TPM_LOG_TPM2) +# if CONFIG(TPM_HASH_SHA1) +# define TPM_MEASURE_ALGO VB2_HASH_SHA1 +# endif +# if CONFIG(TPM_HASH_SHA256) +# define TPM_MEASURE_ALGO VB2_HASH_SHA256 +# endif +# if CONFIG(TPM_HASH_SHA384) +# define TPM_MEASURE_ALGO VB2_HASH_SHA384 +# endif +# if CONFIG(TPM_HASH_SHA512) +# define TPM_MEASURE_ALGO VB2_HASH_SHA512 +# endif #endif #if !defined(TPM_MEASURE_ALGO) diff --git a/src/security/tpm/tspi/log-tpm2.c b/src/security/tpm/tspi/log-tpm2.c new file mode 100644 index 0000000..897cced --- /dev/null +++ b/src/security/tpm/tspi/log-tpm2.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Unlike log.c this implements TPM log according to TPM2.0 specification + * rather then using coreboot-specific log format. + * + * First entry is in TPM1.2 format and serves as a header, the rest are in + * a newer (agile) format which supports SHA256 and multiple hashes, but we + * store only one hash. + * + * This is defined in "TCG EFI Protocol Specification". + */ + +#include <endian.h> +#include <console/console.h> +#include <security/tpm/tspi.h> +#include <security/tpm/tspi/crtm.h> +#include <security/tpm/tspi/logs.h> +#include <region_file.h> +#include <string.h> +#include <symbols.h> +#include <cbmem.h> +#include <vb2_sha.h> + +static uint16_t tpmalg_from_vb2_hash(enum vb2_hash_algorithm hash_type) +{ + switch (hash_type) { + case VB2_HASH_SHA1: + return TPM2_ALG_SHA1; + case VB2_HASH_SHA256: + return TPM2_ALG_SHA256; + case VB2_HASH_SHA384: + return TPM2_ALG_SHA384; + case VB2_HASH_SHA512: + return TPM2_ALG_SHA512; + + default: + return 0xFF; + } +} + +void *tpm2_log_cbmem_init(void) +{ + static struct tpm_2_log_table *tclt; + if (tclt) + return tclt; + + if (cbmem_possibly_online()) { + size_t tpm_log_len; + struct tcg_efi_spec_id_event *hdr; + + tclt = cbmem_find(CBMEM_ID_TPM2_TCG_LOG); + if (tclt) + return tclt; + + tpm_log_len = sizeof(struct tpm_2_log_table) + + MAX_TPM_LOG_ENTRIES * sizeof(struct tpm_2_log_entry); + tclt = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, tpm_log_len); + if (!tclt) + return NULL; + + memset(tclt, 0, tpm_log_len); + hdr = &tclt->header; + + hdr->event_type = htole32(EV_NO_ACTION); + hdr->event_size = htole32(33 + sizeof(tclt->vendor)); + strcpy((char *)hdr->signature, TPM_20_SPEC_ID_EVENT_SIGNATURE); + hdr->platform_class = htole32(0x00); // client platform + hdr->spec_version_minor = 0x00; + hdr->spec_version_major = 0x02; + hdr->spec_errata = 0x00; + hdr->uintn_size = 0x02; // 64-bit UINT + hdr->num_of_algorithms = htole32(1); + hdr->digest_sizes[0].alg_id = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); + hdr->digest_sizes[0].digest_size = htole16(vb2_digest_size(TPM_MEASURE_ALGO)); + + tclt->vendor_info_size = sizeof(tclt->vendor); + tclt->vendor.reserved = 0; + tclt->vendor.version_major = TPM_20_LOG_VI_MAJOR; + tclt->vendor.version_minor = TPM_20_LOG_VI_MINOR; + tclt->vendor.magic = htole32(TPM_20_LOG_VI_MAGIC); + tclt->vendor.max_entries = htole16(MAX_TPM_LOG_ENTRIES); + tclt->vendor.num_entries = htole16(0); + tclt->vendor.entry_size = htole32(sizeof(struct tpm_2_log_entry)); + } + + return tclt; +} + +void tpm2_log_dump(void) +{ + int i, j; + struct tpm_2_log_table *tclt; + int hash_size; + const char *alg_name; + + tclt = tpm_log_init(); + if (!tclt) + return; + + hash_size = vb2_digest_size(TPM_MEASURE_ALGO); + alg_name = vb2_get_hash_algorithm_name(TPM_MEASURE_ALGO); + + printk(BIOS_INFO, "coreboot TPM 2.0 measurements:\n\n"); + for (i = 0; i < le16toh(tclt->vendor.num_entries); i++) { + struct tpm_2_log_entry *tce = &tclt->entries[i]; + + printk(BIOS_INFO, " PCR-%u ", le32toh(tce->pcr)); + + for (j = 0; j < hash_size; j++) + printk(BIOS_INFO, "%02x", tce->digest[j]); + + printk(BIOS_INFO, " %s [%s]\n", alg_name, tce->data); + } + printk(BIOS_INFO, "\n"); +} + +void tpm2_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len) +{ + struct tpm_2_log_table *tclt; + struct tpm_2_log_entry *tce; + + tclt = tpm_log_init(); + if (!tclt) { + printk(BIOS_WARNING, "TPM LOG: non-existent!\n"); + return; + } + + if (!name) { + printk(BIOS_WARNING, "TPM LOG: entry name not set\n"); + return; + } + + if (digest_algo != TPM_MEASURE_ALGO) { + printk(BIOS_WARNING, "TPM LOG: digest is of unsupported type: %s\n", + vb2_get_hash_algorithm_name(digest_algo)); + return; + } + + if (digest_len != vb2_digest_size(TPM_MEASURE_ALGO)) { + printk(BIOS_WARNING, "TPM LOG: digest has invalid length: %d\n", + (int)digest_len); + return; + } + + if (le16toh(tclt->vendor.num_entries) >= le16toh(tclt->vendor.max_entries)) { + printk(BIOS_WARNING, "TPM LOG: log table is full\n"); + return; + } + + tce = &tclt->entries[le16toh(tclt->vendor.num_entries)]; + tclt->vendor.num_entries = htole16(le16toh(tclt->vendor.num_entries) + 1); + + tce->pcr = htole32(pcr); + tce->event_type = htole32(EV_ACTION); + + tce->digest_count = htole32(1); + tce->digest_type = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); + memcpy(tce->digest, digest, vb2_digest_size(TPM_MEASURE_ALGO)); + + tce->data_length = htole32(sizeof(tce->data)); + strncpy((char *)tce->data, name, sizeof(tce->data) - 1); + tce->data[sizeof(tce->data) - 1] = '\0'; +} + +int tpm2_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name) +{ + struct tpm_2_log_table *tclt; + struct tpm_2_log_entry *tce; + + tclt = tpm_log_init(); + if (!tclt) + return 1; + + if (entry_idx < 0 || entry_idx >= le16toh(tclt->vendor.num_entries)) + return 1; + + tce = &tclt->entries[entry_idx]; + + *pcr = le32toh(tce->pcr); + *digest_data = tce->digest; + *digest_algo = TPM_MEASURE_ALGO; /* We validate algorithm on addition */ + *event_name = (char *)tce->data; + return 0; +} + +uint16_t tpm2_log_get_size(const void *log_table) +{ + const struct tpm_2_log_table *tclt = log_table; + return le16toh(tclt->vendor.num_entries); +} + +void tpm2_preram_log_clear(void) +{ + printk(BIOS_INFO, "TPM LOG: clearing the log\n"); + /* + * Pre-RAM log is only for internal use and isn't exported anywhere, hence it's header + * is not initialized. + */ + struct tpm_2_log_table *tclt = (struct tpm_2_log_table *)_tpm_log; + tclt->vendor.max_entries = htole16(MAX_TPM_LOG_ENTRIES); + tclt->vendor.num_entries = htole16(0); +} + +void tpm2_log_copy_entries(const void *from, void *to) +{ + const struct tpm_2_log_table *from_log = from; + struct tpm_2_log_table *to_log = to; + int i; + + for (i = 0; i < le16toh(from_log->vendor.num_entries); i++) { + struct tpm_2_log_entry *tce = + &to_log->entries[le16toh(to_log->vendor.num_entries)]; + to_log->vendor.num_entries = htole16(le16toh(to_log->vendor.num_entries) + 1); + + tce->pcr = from_log->entries[i].pcr; + tce->event_type = from_log->entries[i].event_type; + + tce->digest_count = from_log->entries[i].digest_count; + tce->digest_type = from_log->entries[i].digest_type; + memcpy(tce->digest, from_log->entries[i].digest, sizeof(tce->digest)); + + tce->data_length = from_log->entries[i].data_length; + memcpy(tce->data, from_log->entries[i].data, sizeof(tce->data)); + } +} diff --git a/src/security/tpm/tspi/logs.h b/src/security/tpm/tspi/logs.h index 4170176..2d802f0 100644 --- a/src/security/tpm/tspi/logs.h +++ b/src/security/tpm/tspi/logs.h @@ -36,4 +36,19 @@ const size_t digest_len); void tpm1_log_dump(void); +/* TPM 2.0 log format */ + +void *tpm2_log_init(void); +void *tpm2_log_cbmem_init(void); +void tpm2_preram_log_clear(void); +uint16_t tpm2_log_get_size(const void *log_table); +void tpm2_log_copy_entries(const void *from, void *to); +int tpm2_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name); +void tpm2_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len); +void tpm2_log_dump(void); + #endif /* LOGS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Gerrit-Change-Number: 68748 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: security/tpm: add TPM log format as per 1.2 spec
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68747 ) Change subject: security/tpm: add TPM log format as per 1.2 spec ...................................................................... security/tpm: add TPM log format as per 1.2 spec Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68747 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h A src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm1_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm1.c M src/security/tpm/tspi/log.c A src/security/tpm/tspi/logs.h M src/security/tpm/tspi/tspi.c 11 files changed, 414 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 89f88b7..fa5c8d9 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -60,10 +60,10 @@ #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #define CBMEM_ID_STAGEx_RAW 0x57a9e200 #define CBMEM_ID_STORAGE_DATA 0x53746f72 -#define CBMEM_ID_TPM_CB_LOG 0x54435041 -#define CBMEM_ID_TCPA_TCG_LOG 0x54445041 +#define CBMEM_ID_TPM_CB_LOG 0x54435041 /* TPM log in coreboot-specific format */ +#define CBMEM_ID_TCPA_TCG_LOG 0x54445041 /* TPM log per TPM 1.2 specification */ #define CBMEM_ID_TIMESTAMP 0x54494d45 -#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 +#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 /* TPM log per TPM 2.0 specification */ #define CBMEM_ID_TPM_PPI 0x54505049 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h b/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h new file mode 100644 index 0000000..a45a212 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/tpm_log_defs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef COMMONLIB_BSD_TPM_LOG_DEFS_H +#define COMMONLIB_BSD_TPM_LOG_DEFS_H + +#include <commonlib/helpers.h> +#include <stdint.h> + +#define TCPA_SPEC_ID_EVENT_SIGNATURE "Spec ID Event00" +#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE "Spec ID Event03" + +#define EV_PREBOOT_CERT 0x00000000 +#define EV_POST_CODE 0x00000001 +#define EV_UNUSED 0x00000002 +#define EV_NO_ACTION 0x00000003 +#define EV_SEPARATOR 0x00000004 +#define EV_ACTION 0x00000005 +#define EV_EVENT_TAG 0x00000006 +#define EV_S_CRTM_CONTENTS 0x00000007 +#define EV_S_CRTM_VERSION 0x00000008 +#define EV_CPU_MICROCODE 0x00000009 +#define EV_PLATFORM_CONFIG_FLAGS 0x0000000A +#define EV_TABLE_OF_DEVICES 0x0000000B +#define EV_COMPACT_HASH 0x0000000C +#define EV_IPL 0x0000000D +#define EV_IPL_PARTITION_DATA 0x0000000E +#define EV_NONHOST_CODE 0x0000000F +#define EV_NONHOST_CONFIG 0x00000010 +#define EV_NONHOST_INFO 0x00000011 +#define EV_OMIT_BOOT_DEVICE_EVENTS 0x00000012 + +struct spec_id_event_data { + char signature[16]; + uint32_t platform_class; + uint8_t spec_version_minor; + uint8_t spec_version_major; + uint8_t spec_errata; + uint8_t reserved; + uint8_t vendor_info_size; +} __packed; + +#endif diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 5bc817d..467773d 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -97,12 +97,19 @@ choice prompt "TPM event log format" depends on TPM_MEASURED_BOOT + default TPM_LOG_TPM1 if TPM1 default TPM_LOG_CB config TPM_LOG_CB bool "coreboot's custom format" help Custom coreboot-specific format of the log derived from TPM1 log format. +config TPM_LOG_TPM1 + bool "TPM 1.2 format" + depends on TPM1 + help + Log per TPM 1.2 specification. + See "TCG PC Client Specific Implementation Specification for Conventional BIOS". endchoice diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 7083c00..a8c25d6 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -61,4 +61,10 @@ postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c +ramstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c +romstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c +verstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c +postcar-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c +bootblock-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c + endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tpm1_log_serialized.h b/src/security/tpm/tpm1_log_serialized.h new file mode 100644 index 0000000..a8b7a60 --- /dev/null +++ b/src/security/tpm/tpm1_log_serialized.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __TPM1_LOG_SERIALIZED_H__ +#define __TPM1_LOG_SERIALIZED_H__ + +#include <commonlib/bsd/helpers.h> +#include <commonlib/bsd/tpm_log_defs.h> +#include <stdint.h> + +#define TPM_1_LOG_DIGEST_MAX_LENGTH 20 +#define TPM_1_LOG_DATA_MAX_LENGTH 50 + +#define TPM_1_LOG_VI_MAGIC 0x31544243 /* "CBT1" in LE */ +#define TPM_1_LOG_VI_MAJOR 1 +#define TPM_1_LOG_VI_MINOR 0 + +struct tpm_1_log_entry { + uint32_t pcr; + uint32_t event_type; + uint8_t digest[TPM_1_LOG_DIGEST_MAX_LENGTH]; + uint32_t data_length; + uint8_t data[TPM_1_LOG_DATA_MAX_LENGTH]; +} __packed; + +struct tpm_1_vendor { + uint8_t reserved; + uint8_t version_major; + uint8_t version_minor; + uint32_t magic; + uint16_t max_entries; + uint16_t num_entries; + uint32_t entry_size; +} __packed; + +struct tpm_1_log_table { + /* The first entry of the log is inlined and describes the log itself */ + uint32_t pcr; + uint32_t event_type; + uint8_t digest[TPM_1_LOG_DIGEST_MAX_LENGTH]; + uint32_t spec_id_size; + struct spec_id_event_data spec_id; + struct tpm_1_vendor vendor; + + struct tpm_1_log_entry entries[0]; /* Variable number of entries */ +} __packed; + +#endif diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index b081439..5de0aa2 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -3,6 +3,8 @@ #ifndef TSPI_H_ #define TSPI_H_ +#include <security/tpm/tpm1_log_serialized.h> +#include <security/tpm/tspi/logs.h> #include <security/tpm/tss.h> #include <commonlib/tpm_log_serialized.h> #include <commonlib/region.h> @@ -24,29 +26,62 @@ * Get the pointer to the single CBMEM instance of global * TPM log data, and initialize it when necessary */ -void *tpm_log_cbmem_init(void); +static inline void *tpm_log_cbmem_init(void) +{ + if (CONFIG(TPM_LOG_CB)) + return tpm_cb_log_cbmem_init(); + if (CONFIG(TPM_LOG_TPM1)) + return tpm1_log_cbmem_init(); + return NULL; +} /** * Clears the pre-RAM TPM log data and initializes * any content with default values */ -void tpm_preram_log_clear(void); +static inline void tpm_preram_log_clear(void) +{ + if (CONFIG(TPM_LOG_CB)) + tpm_cb_preram_log_clear(); + else if (CONFIG(TPM_LOG_TPM1)) + tpm1_preram_log_clear(); +} /** * Retrieves number of entries currently stored in the log. */ -uint16_t tpm_log_get_size(const void *log_table); +static inline uint16_t tpm_log_get_size(const void *log_table) +{ + if (CONFIG(TPM_LOG_CB)) + return tpm_cb_log_get_size(log_table); + if (CONFIG(TPM_LOG_TPM1)) + return tpm1_log_get_size(log_table); + return 0; +} /** * Copies data from pre-RAM TPM log to CBMEM (RAM) log */ -void tpm_log_copy_entries(const void *from, void *to); +static inline void tpm_log_copy_entries(const void *from, void *to) +{ + if (CONFIG(TPM_LOG_CB)) + tpm_cb_log_copy_entries(from, to); + else if (CONFIG(TPM_LOG_TPM1)) + tpm1_log_copy_entries(from, to); +} /** * Retrieves an entry from a log. Returns non-zero on invalid index or error. */ -int tpm_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, - enum vb2_hash_algorithm *digest_algo, const char **event_name); +static inline int tpm_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name) +{ + if (CONFIG(TPM_LOG_CB)) + return tpm_cb_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); + if (CONFIG(TPM_LOG_TPM1)) + return tpm1_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); + return 1; +} /** * Add table entry for cbmem TPM log. @@ -56,15 +91,27 @@ * @param digest sets the hash extended into the tpm * @param digest_len the length of the digest */ -void tpm_log_add_table_entry(const char *name, const uint32_t pcr, - enum vb2_hash_algorithm digest_algo, - const uint8_t *digest, - const size_t digest_len); +static inline void tpm_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len) +{ + if (CONFIG(TPM_LOG_CB)) + tpm_cb_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); + else if (CONFIG(TPM_LOG_TPM1)) + tpm1_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); +} /** * Dump TPM log entries on console */ -void tpm_log_dump(void *unused); +static inline void tpm_log_dump(void *unused) +{ + if (CONFIG(TPM_LOG_CB)) + tpm_cb_log_dump(); + else if (CONFIG(TPM_LOG_TPM1)) + tpm1_log_dump(); +} /** * Ask vboot for a digest and extend a TPM PCR with it. diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 97ef09a..2416077 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -20,6 +20,8 @@ # define TPM_MEASURE_ALGO VB2_HASH_SHA1 #elif CONFIG(TPM_LOG_CB) && CONFIG(TPM2) # define TPM_MEASURE_ALGO VB2_HASH_SHA256 +#elif CONFIG(TPM_LOG_TPM1) +# define TPM_MEASURE_ALGO VB2_HASH_SHA1 #endif #if !defined(TPM_MEASURE_ALGO) diff --git a/src/security/tpm/tspi/log-tpm1.c b/src/security/tpm/tspi/log-tpm1.c new file mode 100644 index 0000000..5294426 --- /dev/null +++ b/src/security/tpm/tspi/log-tpm1.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Unlike log.c this implements TPM log according to TPM1.2 specification + * rather than using coreboot-specific log format. + */ + +#include <endian.h> +#include <console/console.h> +#include <security/tpm/tspi/logs.h> +#include <security/tpm/tspi.h> +#include <string.h> +#include <symbols.h> +#include <cbmem.h> +#include <vb2_sha.h> + +void *tpm1_log_cbmem_init(void) +{ + static struct tpm_1_log_table *tclt; + if (tclt) + return tclt; + + if (cbmem_possibly_online()) { + size_t tpm_log_len; + struct spec_id_event_data *hdr; + + tclt = cbmem_find(CBMEM_ID_TCPA_TCG_LOG); + if (tclt) + return tclt; + + tpm_log_len = sizeof(*tclt) + MAX_TPM_LOG_ENTRIES * sizeof(tclt->entries[0]); + tclt = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, tpm_log_len); + if (!tclt) + return NULL; + + memset(tclt, 0, sizeof(*tclt)); + hdr = &tclt->spec_id; + + /* Fill in first "header" entry. */ + tclt->event_type = htole32(EV_NO_ACTION); + tclt->spec_id_size = htole32(sizeof(tclt->spec_id) + sizeof(tclt->vendor)); + strcpy(hdr->signature, TCPA_SPEC_ID_EVENT_SIGNATURE); + hdr->platform_class = htole32(0x00); // client platform + hdr->spec_version_minor = 0x02; + hdr->spec_version_major = 0x01; + hdr->spec_errata = 0x01; + hdr->vendor_info_size = sizeof(tclt->vendor); + + tclt->vendor.reserved = 0; + tclt->vendor.version_major = TPM_1_LOG_VI_MAJOR; + tclt->vendor.version_minor = TPM_1_LOG_VI_MINOR; + tclt->vendor.magic = htole32(TPM_1_LOG_VI_MAGIC); + tclt->vendor.max_entries = htole16(MAX_TPM_LOG_ENTRIES); + tclt->vendor.num_entries = htole16(0); + tclt->vendor.entry_size = htole32(sizeof(tclt->entries[0])); + } + + return tclt; +} + +void tpm1_log_dump(void) +{ + int i, j; + struct tpm_1_log_table *tclt; + + tclt = tpm_log_init(); + if (!tclt) + return; + + printk(BIOS_INFO, "coreboot TPM 1.2 measurements:\n\n"); + for (i = 0; i < le16toh(tclt->vendor.num_entries); i++) { + struct tpm_1_log_entry *tce = &tclt->entries[i]; + + printk(BIOS_INFO, " PCR-%u ", le32toh(tce->pcr)); + + for (j = 0; j < TPM_1_LOG_DIGEST_MAX_LENGTH; j++) + printk(BIOS_INFO, "%02x", tce->digest[j]); + + printk(BIOS_INFO, " %s [%s]\n", "SHA1", (char *)tce->data); + } + printk(BIOS_INFO, "\n"); +} + +void tpm1_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len) +{ + struct tpm_1_log_table *tclt; + struct tpm_1_log_entry *tce; + + tclt = tpm_log_init(); + if (!tclt) { + printk(BIOS_WARNING, "TPM LOG: non-existent!\n"); + return; + } + + if (!name) { + printk(BIOS_WARNING, "TPM LOG: entry name not set\n"); + return; + } + + if (digest_algo != VB2_HASH_SHA1) { + printk(BIOS_WARNING, "TPM LOG: unsupported hash algorithm\n"); + return; + } + + if (le16toh(tclt->vendor.num_entries) >= le16toh(tclt->vendor.max_entries)) { + printk(BIOS_WARNING, "TPM LOG: log table is full\n"); + return; + } + + tce = &tclt->entries[le16toh(tclt->vendor.num_entries)]; + tclt->vendor.num_entries = htole16(le16toh(tclt->vendor.num_entries) + 1); + + tce->pcr = htole32(pcr); + tce->event_type = htole32(EV_ACTION); + + memcpy(tce->digest, digest, digest_len); + + tce->data_length = htole32(TPM_1_LOG_DATA_MAX_LENGTH); + strncpy((char *)tce->data, name, sizeof(tce->data) - 1); + tce->data[sizeof(tce->data) - 1] = '\0'; +} + +void tpm1_preram_log_clear(void) +{ + printk(BIOS_INFO, "TPM LOG: clearing the log\n"); + /* + * Pre-RAM log is only for internal use and isn't exported anywhere, hence it's header + * is not initialized. + */ + struct tpm_1_log_table *tclt = (struct tpm_1_log_table *)_tpm_log; + tclt->vendor.max_entries = htole16(MAX_TPM_LOG_ENTRIES); + tclt->vendor.num_entries = htole16(0); +} + +int tpm1_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name) +{ + struct tpm_1_log_table *tclt; + struct tpm_1_log_entry *tce; + + tclt = tpm_log_init(); + if (!tclt) + return 1; + + if (entry_idx < 0 || entry_idx >= le16toh(tclt->vendor.num_entries)) + return 1; + + tce = &tclt->entries[entry_idx]; + + *pcr = le32toh(tce->pcr); + *digest_data = tce->digest; + *digest_algo = VB2_HASH_SHA1; + *event_name = (char *)tce->data; + return 0; +} + +uint16_t tpm1_log_get_size(const void *log_table) +{ + const struct tpm_1_log_table *tclt = log_table; + return le16toh(tclt->vendor.num_entries); +} + +void tpm1_log_copy_entries(const void *from, void *to) +{ + const struct tpm_1_log_table *from_log = from; + struct tpm_1_log_table *to_log = to; + int i; + + for (i = 0; i < le16toh(from_log->vendor.num_entries); i++) { + struct tpm_1_log_entry *tce = + &to_log->entries[le16toh(to_log->vendor.num_entries)]; + memcpy(tce, &from_log->entries[i], sizeof(*tce)); + + to_log->vendor.num_entries = htole16(le16toh(to_log->vendor.num_entries) + 1); + } +} diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index e33cacb..086aceb 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <security/tpm/tspi/logs.h> #include <security/tpm/tspi.h> #include <region_file.h> #include <string.h> @@ -8,7 +9,7 @@ #include <cbmem.h> #include <vb2_sha.h> -void *tpm_log_cbmem_init(void) +void *tpm_cb_log_cbmem_init(void) { static struct tpm_cb_log_table *tclt; if (tclt) @@ -29,7 +30,7 @@ return tclt; } -void tpm_log_dump(void *unused) +void tpm_cb_log_dump(void) { int i, j; struct tpm_cb_log_table *tclt; @@ -54,10 +55,10 @@ printk(BIOS_INFO, "\n"); } -void tpm_log_add_table_entry(const char *name, const uint32_t pcr, - enum vb2_hash_algorithm digest_algo, - const uint8_t *digest, - const size_t digest_len) +void tpm_cb_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len) { struct tpm_cb_log_table *tclt = tpm_log_init(); if (!tclt) { @@ -93,7 +94,7 @@ memcpy(tce->digest, digest, tce->digest_length); } -void tpm_preram_log_clear(void) +void tpm_cb_preram_log_clear(void) { printk(BIOS_INFO, "TPM LOG: clearing preram log\n"); struct tpm_cb_log_table *tclt = (struct tpm_cb_log_table *)_tpm_log; @@ -101,8 +102,8 @@ tclt->num_entries = 0; } -int tpm_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, - enum vb2_hash_algorithm *digest_algo, const char **event_name) +int tpm_cb_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name) { struct tpm_cb_log_table *tclt; struct tpm_cb_log_entry *tce; @@ -131,13 +132,13 @@ return 0; } -uint16_t tpm_log_get_size(const void *log_table) +uint16_t tpm_cb_log_get_size(const void *log_table) { const struct tpm_cb_log_table *tclt = log_table; return tclt->num_entries; } -void tpm_log_copy_entries(const void *from, void *to) +void tpm_cb_log_copy_entries(const void *from, void *to) { const struct tpm_cb_log_table *from_log = from; struct tpm_cb_log_table *to_log = to; diff --git a/src/security/tpm/tspi/logs.h b/src/security/tpm/tspi/logs.h new file mode 100644 index 0000000..4170176 --- /dev/null +++ b/src/security/tpm/tspi/logs.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef LOGS_H_ +#define LOGS_H_ + +#include <stdint.h> +#include <vb2_api.h> + +/* coreboot-specific TPM log format */ + +void *tpm_cb_log_init(void); +void *tpm_cb_log_cbmem_init(void); +void tpm_cb_preram_log_clear(void); +uint16_t tpm_cb_log_get_size(const void *log_table); +void tpm_cb_log_copy_entries(const void *from, void *to); +int tpm_cb_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name); +void tpm_cb_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len); +void tpm_cb_log_dump(void); + +/* TPM 1.2 log format */ + +void *tpm1_log_init(void); +void *tpm1_log_cbmem_init(void); +void tpm1_preram_log_clear(void); +uint16_t tpm1_log_get_size(const void *log_table); +void tpm1_log_copy_entries(const void *from, void *to); +int tpm1_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, + enum vb2_hash_algorithm *digest_algo, const char **event_name); +void tpm1_log_add_table_entry(const char *name, const uint32_t pcr, + enum vb2_hash_algorithm digest_algo, + const uint8_t *digest, + const size_t digest_len); +void tpm1_log_dump(void); + +#endif /* LOGS_H_ */ diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 3be98a2..a771d2a 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <security/tpm/tspi/crtm.h> +#include <security/tpm/tspi/logs.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <assert.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/68747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Gerrit-Change-Number: 68747 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2023