coreboot-gerrit March 2023

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[S] Change in coreboot[master]: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/73217/comment/5343fccc_7b51f2f9 PS8, Line 19: EC_HOST_EVENT_GPU > no, i had a look at some of the other baseboards and the […] For sure we could wrap this mask in another ifdef here if we feel its absolutely needed. That said, this existing in "Brya" baseboard is likely shorter lived. This can be dropped when we move away from Agah variant in favor of Hades baseboard & variant. In this case, all Hades baseboard variants will want to have this event. -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 21:02:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: PS8: > i think `baseboard/skolas/include/baseboard/ec.h` needs the same treatment. […] skolas is being dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 20:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU
by Caveh Jalali (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Tarun Tuli, Nick Vaccaro. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 8: (2 comments) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: PS8: i think `baseboard/skolas/include/baseboard/ec.h` needs the same treatment. can we just symlink the two files? https://review.coreboot.org/c/coreboot/+/73217/comment/9a6405a5_0bcb7192 PS8, Line 19: EC_HOST_EVENT_GPU > What is the thinking of excluding this mask on some variants? Would we potentially reuse the same b […] no, i had a look at some of the other baseboards and the pattern is to enable what you actually use. we already have a config for dGPU so it seems to make sense to apply it where appropriate. i'm not sure if `INCLUDE_NVIDIA_GPU_ASL` really needs to be specific to either of nvidia or ASL. repurposing event bits is dangerous as we saw on another project (we unintentionally ended up with a wake source). i'd be OK with enabling all the interesting events uniformly across all the baseboards and then trust the EC to not generate events that don't "exist" on a specific board. i'm not sure that's feasible - i don't know the history of how we ended up with custom event masks per baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 20:52:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/adl: Add Raptorlake-HX definitions
by Tim Crawford (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72926 to look at the new patch set (#4). Change subject: soc/intel/adl: Add Raptorlake-HX definitions ...................................................................... soc/intel/adl: Add Raptorlake-HX definitions These definitions allow the Clevo PD50SNE (system76/serw13) to reach the payload. Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.5) Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/mainboard/intel/adlrvp/mainboard.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 12 files changed, 148 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72926/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Gerrit-Change-Number: 72926 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/skyrim: Allow port descriptors to be overridden
by build bot (Jenkins) (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73294 ) Change subject: mb/google/skyrim: Allow port descriptors to be overridden ...................................................................... Patch Set 2: Verified+1 (1 comment) File src/mainboard/google/skyrim/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171421): https://review.coreboot.org/c/coreboot/+/73294/comment/7a52652e_f25ea7ed PS2, Line 97: if (!*dxio_num || !*dxio_descs) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/73294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Gerrit-Change-Number: 73294 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 20:33:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Enable L1 ASPM substates for PCIe devices
by Matt DeVillier (Code Review) 03 Mar '23

03 Mar '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73438 ) Change subject: mb/google/skyrim: Enable L1 ASPM substates for PCIe devices ...................................................................... mb/google/skyrim: Enable L1 ASPM substates for PCIe devices Enable both L1.1 and L1.2 substates for the WiFi, SD card reader, and SSD (both NVMe and eMMC). If a given device does not support a particular substate, then it will not be enabled during PCIe enumeration by coreboot. The link_hotplug setting is unused on Mendocino, so remove it while we're here, as code cleanup. This has no functional difference. BUG=b:270690572 TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different storage configs, verify WiFi/SD card/SSD all functional and have L1 substates enabled insofar as they are supported by the device. Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/73438/1 diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index d745bd7..20032b2 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -16,7 +16,8 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true .clk_req = CLK_REQ2, }, { /* SD */ @@ -29,7 +30,8 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true .gpio_group_id = GPIO_27, .clk_req = CLK_REQ1, }, @@ -43,7 +45,8 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true .gpio_group_id = GPIO_6, .clk_req = CLK_REQ0, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/73438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Gerrit-Change-Number: 73438 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/adl: Add Raptorlake-HX definitions
by Tim Crawford (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72926 to look at the new patch set (#3). Change subject: soc/intel/adl: Add Raptorlake-HX definitions ...................................................................... soc/intel/adl: Add Raptorlake-HX definitions These definitions allow the Clevo PD50SNE (system76/oryp11) to reach the payload. Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.5) Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/mainboard/intel/adlrvp/mainboard.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 12 files changed, 148 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72926/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Gerrit-Change-Number: 72926 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/common: Add RPP-S PCI IDs
by Tim Crawford (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jeremy Soller. Hello Jeremy Soller, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/73437 to review the following change. Change subject: soc/intel/common: Add RPP-S PCI IDs ...................................................................... soc/intel/common: Add RPP-S PCI IDs Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xdci/xdci.c 13 files changed, 142 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/73437/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d6548ce..cd4d0ee 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3467,6 +3467,35 @@ #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d +#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 +#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 +#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a +#define PCI_DID_INTEL_RPP_S_PCIE_RP4 0x7a3b +#define PCI_DID_INTEL_RPP_S_PCIE_RP5 0x7a3c +#define PCI_DID_INTEL_RPP_S_PCIE_RP6 0x7a3d +#define PCI_DID_INTEL_RPP_S_PCIE_RP7 0x7a3e +#define PCI_DID_INTEL_RPP_S_PCIE_RP8 0x7a3f +#define PCI_DID_INTEL_RPP_S_PCIE_RP9 0x7a30 +#define PCI_DID_INTEL_RPP_S_PCIE_RP10 0x7a31 +#define PCI_DID_INTEL_RPP_S_PCIE_RP11 0x7a32 +#define PCI_DID_INTEL_RPP_S_PCIE_RP12 0x7a33 +#define PCI_DID_INTEL_RPP_S_PCIE_RP13 0x7a34 +#define PCI_DID_INTEL_RPP_S_PCIE_RP14 0x7a35 +#define PCI_DID_INTEL_RPP_S_PCIE_RP15 0x7a36 +#define PCI_DID_INTEL_RPP_S_PCIE_RP16 0x7a37 +#define PCI_DID_INTEL_RPP_S_PCIE_RP17 0x7a40 +#define PCI_DID_INTEL_RPP_S_PCIE_RP18 0x7a41 +#define PCI_DID_INTEL_RPP_S_PCIE_RP19 0x7a42 +#define PCI_DID_INTEL_RPP_S_PCIE_RP20 0x7a43 +#define PCI_DID_INTEL_RPP_S_PCIE_RP21 0x7a44 +#define PCI_DID_INTEL_RPP_S_PCIE_RP22 0x7a45 +#define PCI_DID_INTEL_RPP_S_PCIE_RP23 0x7a46 +#define PCI_DID_INTEL_RPP_S_PCIE_RP24 0x7a47 +#define PCI_DID_INTEL_RPP_S_PCIE_RP25 0x7a48 +#define PCI_DID_INTEL_RPP_S_PCIE_RP26 0x7a49 +#define PCI_DID_INTEL_RPP_S_PCIE_RP27 0x7a4a +#define PCI_DID_INTEL_RPP_S_PCIE_RP28 0x7a4b + /* Intel SATA device Ids */ #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 @@ -3553,6 +3582,7 @@ #define PCI_DID_INTEL_MTL_SATA 0x7e63 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 +#define PCI_DID_INTEL_RPP_S_SATA 0x7a62 /* Intel PMC device Ids */ #define PCI_DID_INTEL_SPT_LP_PMC 0x9d21 @@ -3688,6 +3718,13 @@ #define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5 #define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6 +#define PCI_DID_INTEL_RPP_S_I2C0 0x7a4c +#define PCI_DID_INTEL_RPP_S_I2C1 0x7a4d +#define PCI_DID_INTEL_RPP_S_I2C2 0x7a4e +#define PCI_DID_INTEL_RPP_S_I2C3 0x7a4f +#define PCI_DID_INTEL_RPP_S_I2C4 0x7a7c +#define PCI_DID_INTEL_RPP_S_I2C5 0x7a7d + #define PCI_DID_INTEL_MTL_I2C0 0x7e78 #define PCI_DID_INTEL_MTL_I2C1 0x7e79 #define PCI_DID_INTEL_MTL_I2C2 0x7e7a @@ -3765,6 +3802,11 @@ #define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7 #define PCI_DID_INTEL_ADP_M_N_UART3 0x54da +#define PCI_DID_INTEL_RPP_S_UART0 0x7a28 +#define PCI_DID_INTEL_RPP_S_UART1 0x7a29 +#define PCI_DID_INTEL_RPP_S_UART2 0x7a7e +#define PCI_DID_INTEL_RPP_S_UART3 0x7a5c + #define PCI_DID_INTEL_MTL_UART0 0x7e25 #define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART2 0x7e52 @@ -3850,6 +3892,12 @@ #define PCI_DID_INTEL_ADP_M_N_SPI1 0x54ab #define PCI_DID_INTEL_ADP_M_SPI2 0x54fb +#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI 0x7a24 +#define PCI_DID_INTEL_RPP_S_SPI0 0x7a2a +#define PCI_DID_INTEL_RPP_S_SPI1 0x7a2b +#define PCI_DID_INTEL_RPP_S_SPI2 0x7a7b +#define PCI_DID_INTEL_RPP_S_SPI3 0x7a79 + #define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca #define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23 @@ -4165,6 +4213,7 @@ #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 +#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4204,6 +4253,7 @@ #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e +#define PCI_DID_INTEL_RPP_S_TCSS_XHCI 0x7a60 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4274,6 +4324,14 @@ #define PCI_DID_INTEL_ADP_S_AUDIO_8 0x7ad7 #define PCI_DID_INTEL_ADP_P_AUDIO 0x51c8 #define PCI_DID_INTEL_RPP_P_AUDIO 0x51ca +#define PCI_DID_INTEL_RPP_S_AUDIO_1 0x7a50 +#define PCI_DID_INTEL_RPP_S_AUDIO_2 0x7a51 +#define PCI_DID_INTEL_RPP_S_AUDIO_3 0x7a52 +#define PCI_DID_INTEL_RPP_S_AUDIO_4 0x7a53 +#define PCI_DID_INTEL_RPP_S_AUDIO_5 0x7a54 +#define PCI_DID_INTEL_RPP_S_AUDIO_6 0x7a55 +#define PCI_DID_INTEL_RPP_S_AUDIO_7 0x7a56 +#define PCI_DID_INTEL_RPP_S_AUDIO_8 0x7a57 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1 0x54c8 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2 0x54c9 @@ -4354,6 +4412,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_RPP_S_XDCI 0x7a61 /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 @@ -4494,6 +4553,10 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 +#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73 /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 5509df2..fed95492 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -54,6 +54,10 @@ PCI_DID_INTEL_ADL_N_CNVI_WIFI_1, PCI_DID_INTEL_ADL_N_CNVI_WIFI_2, PCI_DID_INTEL_ADL_N_CNVI_WIFI_3, + PCI_DID_INTEL_RPL_S_CNVI_WIFI_0, + PCI_DID_INTEL_RPL_S_CNVI_WIFI_1, + PCI_DID_INTEL_RPL_S_CNVI_WIFI_2, + PCI_DID_INTEL_RPL_S_CNVI_WIFI_3, 0 }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 0229ee5..5419a29 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -22,6 +22,14 @@ PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_RPP_P_AUDIO, + PCI_DID_INTEL_RPP_S_AUDIO_1, + PCI_DID_INTEL_RPP_S_AUDIO_2, + PCI_DID_INTEL_RPP_S_AUDIO_3, + PCI_DID_INTEL_RPP_S_AUDIO_4, + PCI_DID_INTEL_RPP_S_AUDIO_5, + PCI_DID_INTEL_RPP_S_AUDIO_6, + PCI_DID_INTEL_RPP_S_AUDIO_7, + PCI_DID_INTEL_RPP_S_AUDIO_8, PCI_DID_INTEL_APL_AUDIO, PCI_DID_INTEL_CNL_AUDIO, PCI_DID_INTEL_GLK_AUDIO, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4fa10b0..33f9032 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -567,6 +567,7 @@ PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, + PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, 0 diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index c70a61e..fdd78fc 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -30,6 +30,14 @@ PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_RPP_P_AUDIO, + PCI_DID_INTEL_RPP_S_AUDIO_1, + PCI_DID_INTEL_RPP_S_AUDIO_2, + PCI_DID_INTEL_RPP_S_AUDIO_3, + PCI_DID_INTEL_RPP_S_AUDIO_4, + PCI_DID_INTEL_RPP_S_AUDIO_5, + PCI_DID_INTEL_RPP_S_AUDIO_6, + PCI_DID_INTEL_RPP_S_AUDIO_7, + PCI_DID_INTEL_RPP_S_AUDIO_8, PCI_DID_INTEL_APL_AUDIO, PCI_DID_INTEL_GLK_AUDIO, PCI_DID_INTEL_LWB_AUDIO, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 70c7e18..141b66e 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -271,6 +271,12 @@ PCI_DID_INTEL_ADP_M_N_I2C3, PCI_DID_INTEL_ADP_M_N_I2C4, PCI_DID_INTEL_ADP_M_N_I2C5, + PCI_DID_INTEL_RPP_S_I2C0, + PCI_DID_INTEL_RPP_S_I2C1, + PCI_DID_INTEL_RPP_S_I2C2, + PCI_DID_INTEL_RPP_S_I2C3, + PCI_DID_INTEL_RPP_S_I2C4, + PCI_DID_INTEL_RPP_S_I2C5, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c8a958d..323b140 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -328,6 +328,34 @@ PCI_DID_INTEL_ADP_M_N_PCIE_RP10, PCI_DID_INTEL_ADP_N_PCIE_RP11, PCI_DID_INTEL_ADP_N_PCIE_RP12, + PCI_DID_INTEL_RPP_S_PCIE_RP1, + PCI_DID_INTEL_RPP_S_PCIE_RP2, + PCI_DID_INTEL_RPP_S_PCIE_RP3, + PCI_DID_INTEL_RPP_S_PCIE_RP4, + PCI_DID_INTEL_RPP_S_PCIE_RP5, + PCI_DID_INTEL_RPP_S_PCIE_RP6, + PCI_DID_INTEL_RPP_S_PCIE_RP7, + PCI_DID_INTEL_RPP_S_PCIE_RP8, + PCI_DID_INTEL_RPP_S_PCIE_RP9, + PCI_DID_INTEL_RPP_S_PCIE_RP10, + PCI_DID_INTEL_RPP_S_PCIE_RP11, + PCI_DID_INTEL_RPP_S_PCIE_RP12, + PCI_DID_INTEL_RPP_S_PCIE_RP13, + PCI_DID_INTEL_RPP_S_PCIE_RP14, + PCI_DID_INTEL_RPP_S_PCIE_RP15, + PCI_DID_INTEL_RPP_S_PCIE_RP16, + PCI_DID_INTEL_RPP_S_PCIE_RP17, + PCI_DID_INTEL_RPP_S_PCIE_RP18, + PCI_DID_INTEL_RPP_S_PCIE_RP19, + PCI_DID_INTEL_RPP_S_PCIE_RP20, + PCI_DID_INTEL_RPP_S_PCIE_RP21, + PCI_DID_INTEL_RPP_S_PCIE_RP22, + PCI_DID_INTEL_RPP_S_PCIE_RP23, + PCI_DID_INTEL_RPP_S_PCIE_RP24, + PCI_DID_INTEL_RPP_S_PCIE_RP25, + PCI_DID_INTEL_RPP_S_PCIE_RP26, + PCI_DID_INTEL_RPP_S_PCIE_RP27, + PCI_DID_INTEL_RPP_S_PCIE_RP28, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 190122d..41e31fe 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -16,6 +16,7 @@ PCI_DID_INTEL_MTL_SATA, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, + PCI_DID_INTEL_RPP_S_SATA, PCI_DID_INTEL_LWB_SATA_AHCI, PCI_DID_INTEL_LWB_SSATA_AHCI, PCI_DID_INTEL_LWB_SATA_RAID, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index d482e26..ce98505 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -52,6 +52,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, + PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, PCI_DID_INTEL_GLK_SMBUS, PCI_DID_INTEL_CNL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 93278f1..b95ac96 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -182,6 +182,10 @@ PCI_DID_INTEL_ADP_M_N_SPI0, PCI_DID_INTEL_ADP_M_N_SPI1, PCI_DID_INTEL_ADP_M_SPI2, + PCI_DID_INTEL_RPP_S_SPI0, + PCI_DID_INTEL_RPP_S_SPI1, + PCI_DID_INTEL_RPP_S_SPI2, + PCI_DID_INTEL_RPP_S_SPI3, PCI_DID_INTEL_DNV_SPI, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 76e4bc9..9123498 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -406,6 +406,10 @@ PCI_DID_INTEL_ADP_M_N_UART1, PCI_DID_INTEL_ADP_M_N_UART2, PCI_DID_INTEL_ADP_M_N_UART3, + PCI_DID_INTEL_RPP_S_UART0, + PCI_DID_INTEL_RPP_S_UART1, + PCI_DID_INTEL_RPP_S_UART2, + PCI_DID_INTEL_RPP_S_UART3, 0, }; diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index d1a2dc6..fad918b 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -27,6 +27,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_RPP_P_TCSS_XHCI, + PCI_DID_INTEL_RPP_S_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI, PCI_DID_INTEL_MTL_P_TCSS_XHCI, PCI_DID_INTEL_TGP_TCSS_XHCI, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 495996e..7ee2dbb 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ PCI_DID_INTEL_ADP_P_XDCI, PCI_DID_INTEL_ADP_S_XDCI, PCI_DID_INTEL_ADP_M_XDCI, + PCI_DID_INTEL_RPP_S_XDCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/73437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Gerrit-Change-Number: 73437 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/73217/comment/15d7f808_e58e9525 PS8, Line 19: EC_HOST_EVENT_GPU > we should add a Kconfig for this event (or dGPU in general) […] What is the thinking of excluding this mask on some variants? Would we potentially reuse the same bit for different purposes on different variants in the future? -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Mar 2023 19:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Nico Huber (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Felix Singer, Angel Pons, Keith Hui, Elyes Haouas. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61540 ) Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Patchset: PS7: > Nico, I'm not sure if devicetree covers romstage. […] Looking at the northbridge code, it's actually already possible to specify the SPD addresses in the devicetree. Only they are expected by the MRC path in the wrong notation and the native raminit path seems to ignore them... The chain around CB:32070 is what I remembered btw. I guess it's the right way, but needs somebody with the time to follow it through. -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 03 Mar 2023 19:19:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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