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[L] Change in coreboot[master]: mb/system76: Add custom backlight levels for Intel GMA
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61301 ) Change subject: mb/system76: Add custom backlight levels for Intel GMA ...................................................................... mb/system76: Add custom backlight levels for Intel GMA Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- A src/mainboard/system76/cml-u/acpi/backlight.asl M src/mainboard/system76/cml-u/acpi/mainboard.asl M src/mainboard/system76/cml-u/dsdt.asl A src/mainboard/system76/gaze15/acpi/backlight.asl M src/mainboard/system76/gaze15/acpi/mainboard.asl M src/mainboard/system76/gaze15/dsdt.asl A src/mainboard/system76/kbl-u/acpi/backlight.asl M src/mainboard/system76/kbl-u/acpi/mainboard.asl A src/mainboard/system76/oryp5/acpi/backlight.asl M src/mainboard/system76/oryp5/acpi/mainboard.asl M src/mainboard/system76/oryp5/dsdt.asl A src/mainboard/system76/oryp6/acpi/backlight.asl M src/mainboard/system76/oryp6/acpi/mainboard.asl M src/mainboard/system76/oryp6/dsdt.asl A src/mainboard/system76/tgl-h/acpi/backlight.asl M src/mainboard/system76/tgl-h/acpi/mainboard.asl M src/mainboard/system76/tgl-h/dsdt.asl A src/mainboard/system76/tgl-u/acpi/backlight.asl M src/mainboard/system76/tgl-u/acpi/mainboard.asl M src/mainboard/system76/tgl-u/dsdt.asl A src/mainboard/system76/whl-u/acpi/backlight.asl M src/mainboard/system76/whl-u/acpi/mainboard.asl M src/mainboard/system76/whl-u/dsdt.asl 23 files changed, 291 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/cml-u/acpi/backlight.asl b/src/mainboard/system76/cml-u/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/cml-u/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/cml-u/acpi/mainboard.asl b/src/mainboard/system76/cml-u/acpi/mainboard.asl index 416cc5a..3335ba8 100644 --- a/src/mainboard/system76/cml-u/acpi/mainboard.asl +++ b/src/mainboard/system76/cml-u/acpi/mainboard.asl @@ -6,6 +6,9 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/cml-u/dsdt.asl b/src/mainboard/system76/cml-u/dsdt.asl index 982e226..b633254 100644 --- a/src/mainboard/system76/cml-u/dsdt.asl +++ b/src/mainboard/system76/cml-u/dsdt.asl @@ -19,7 +19,6 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/gaze15/acpi/backlight.asl b/src/mainboard/system76/gaze15/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/gaze15/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl index 4e67439..b235437 100644 --- a/src/mainboard/system76/gaze15/acpi/mainboard.asl +++ b/src/mainboard/system76/gaze15/acpi/mainboard.asl @@ -6,6 +6,9 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/gaze15/dsdt.asl b/src/mainboard/system76/gaze15/dsdt.asl index d2bd57d..a48382b 100644 --- a/src/mainboard/system76/gaze15/dsdt.asl +++ b/src/mainboard/system76/gaze15/dsdt.asl @@ -18,7 +18,6 @@ Device (\_SB.PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/kbl-u/acpi/backlight.asl b/src/mainboard/system76/kbl-u/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/kbl-u/acpi/mainboard.asl b/src/mainboard/system76/kbl-u/acpi/mainboard.asl index 11735e8..a36923f 100644 --- a/src/mainboard/system76/kbl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/kbl-u/acpi/mainboard.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ Scope (\_SB) { + Scope (PCI0) { + #include "backlight.asl" + } + #include "ac.asl" #include "battery.asl" #include "buttons.asl" diff --git a/src/mainboard/system76/oryp5/acpi/backlight.asl b/src/mainboard/system76/oryp5/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/oryp5/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/oryp5/acpi/mainboard.asl b/src/mainboard/system76/oryp5/acpi/mainboard.asl index 4373b2a..17d2221 100644 --- a/src/mainboard/system76/oryp5/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp5/acpi/mainboard.asl @@ -7,6 +7,9 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } Scope (\_GPE) diff --git a/src/mainboard/system76/oryp5/dsdt.asl b/src/mainboard/system76/oryp5/dsdt.asl index 982e226..b633254 100644 --- a/src/mainboard/system76/oryp5/dsdt.asl +++ b/src/mainboard/system76/oryp5/dsdt.asl @@ -19,7 +19,6 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/oryp6/acpi/backlight.asl b/src/mainboard/system76/oryp6/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/oryp6/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/oryp6/acpi/mainboard.asl b/src/mainboard/system76/oryp6/acpi/mainboard.asl index 4e67439..b235437 100644 --- a/src/mainboard/system76/oryp6/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp6/acpi/mainboard.asl @@ -6,6 +6,9 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/oryp6/dsdt.asl b/src/mainboard/system76/oryp6/dsdt.asl index d2bd57d..a48382b 100644 --- a/src/mainboard/system76/oryp6/dsdt.asl +++ b/src/mainboard/system76/oryp6/dsdt.asl @@ -18,7 +18,6 @@ Device (\_SB.PCI0) { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/tgl-h/acpi/backlight.asl b/src/mainboard/system76/tgl-h/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/tgl-h/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/tgl-h/acpi/mainboard.asl b/src/mainboard/system76/tgl-h/acpi/mainboard.asl index 4675bc9..c982a9e 100644 --- a/src/mainboard/system76/tgl-h/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-h/acpi/mainboard.asl @@ -6,4 +6,7 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } diff --git a/src/mainboard/system76/tgl-h/dsdt.asl b/src/mainboard/system76/tgl-h/dsdt.asl index fb40a5d..904073c 100644 --- a/src/mainboard/system76/tgl-h/dsdt.asl +++ b/src/mainboard/system76/tgl-h/dsdt.asl @@ -20,7 +20,6 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/tgl-u/acpi/backlight.asl b/src/mainboard/system76/tgl-u/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/tgl-u/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/tgl-u/acpi/mainboard.asl b/src/mainboard/system76/tgl-u/acpi/mainboard.asl index 4675bc9..c982a9e 100644 --- a/src/mainboard/system76/tgl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-u/acpi/mainboard.asl @@ -6,4 +6,7 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } diff --git a/src/mainboard/system76/tgl-u/dsdt.asl b/src/mainboard/system76/tgl-u/dsdt.asl index fb40a5d..904073c 100644 --- a/src/mainboard/system76/tgl-u/dsdt.asl +++ b/src/mainboard/system76/tgl-u/dsdt.asl @@ -20,7 +20,6 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/system76/whl-u/acpi/backlight.asl b/src/mainboard/system76/whl-u/acpi/backlight.asl new file mode 100644 index 0000000..f020234 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/whl-u/acpi/mainboard.asl b/src/mainboard/system76/whl-u/acpi/mainboard.asl index ade0bb2..2495377 100644 --- a/src/mainboard/system76/whl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/whl-u/acpi/mainboard.asl @@ -6,6 +6,9 @@ Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/whl-u/dsdt.asl b/src/mainboard/system76/whl-u/dsdt.asl index 982e226..b633254 100644 --- a/src/mainboard/system76/whl-u/dsdt.asl +++ b/src/mainboard/system76/whl-u/dsdt.asl @@ -19,7 +19,6 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/61301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Gerrit-Change-Number: 61301 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/system76/tgl-u: Leave TBT LSX0 as FSP configured
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71666 ) Change subject: mb/system76/tgl-u: Leave TBT LSX0 as FSP configured ...................................................................... mb/system76/tgl-u: Leave TBT LSX0 as FSP configured Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/tgl-u/variants/darp7/gpio.c M src/mainboard/system76/tgl-u/variants/galp5/gpio.c M src/mainboard/system76/tgl-u/variants/lemp10/gpio.c 3 files changed, 21 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c index ad18ca6..3e0bc77 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c @@ -137,8 +137,8 @@ PAD_NC(GPP_E15, NONE), // ALERT# PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) PAD_NC(GPP_E20, NONE), // SWI# PAD_NC(GPP_E21, NONE), // DDP2 I2C / TBT_LSX1 strap PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c index 17119b3..7b8e850 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c @@ -131,8 +131,8 @@ PAD_NC(GPP_E15, NONE), // ALERT#_R PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) PAD_NC(GPP_E20, NONE), PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c index cca2056..cd9f833 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c @@ -131,8 +131,8 @@ PAD_CFG_GPI(GPP_E15, DN_20K, DEEP), // SCI# _PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000), // SMI# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) _PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000), // SWI# PAD_NC(GPP_E21, NONE), // GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V) PAD_NC(GPP_E22, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/71666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Gerrit-Change-Number: 71666 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: {ec,mb}/system76: Move smbios_system_wakeup_type
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71802 ) Change subject: {ec,mb}/system76: Move smbios_system_wakeup_type ...................................................................... {ec,mb}/system76: Move smbios_system_wakeup_type Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/ec/system76/ec/Makefile.inc A src/ec/system76/ec/smbios.c M src/mainboard/system76/addw1/ramstage.c M src/mainboard/system76/adl/ramstage.c M src/mainboard/system76/bonw14/ramstage.c M src/mainboard/system76/cml-u/ramstage.c M src/mainboard/system76/gaze15/ramstage.c M src/mainboard/system76/oryp5/ramstage.c M src/mainboard/system76/oryp6/ramstage.c M src/mainboard/system76/tgl-h/ramstage.c M src/mainboard/system76/tgl-u/ramstage.c M src/mainboard/system76/whl-u/ramstage.c 12 files changed, 28 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/ec/system76/ec/Makefile.inc b/src/ec/system76/ec/Makefile.inc index 110b997..9808e29 100644 --- a/src/ec/system76/ec/Makefile.inc +++ b/src/ec/system76/ec/Makefile.inc @@ -2,6 +2,9 @@ ifeq ($(CONFIG_EC_SYSTEM76_EC),y) all-y += system76_ec.c + +ramstage-y += smbios.c + smm-$(CONFIG_DEBUG_SMI) += system76_ec.c endif diff --git a/src/ec/system76/ec/smbios.c b/src/ec/system76/ec/smbios.c new file mode 100644 index 0000000..e55d5f0 --- /dev/null +++ b/src/ec/system76/ec/smbios.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + // TODO: Read wake source from EC. + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} diff --git a/src/mainboard/system76/addw1/ramstage.c b/src/mainboard/system76/addw1/ramstage.c index 376849f..ca6f64b1 100644 --- a/src/mainboard/system76/addw1/ramstage.c +++ b/src/mainboard/system76/addw1/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <variant/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c index 86ce821..c767f2d 100644 --- a/src/mainboard/system76/adl/ramstage.c +++ b/src/mainboard/system76/adl/ramstage.c @@ -2,12 +2,6 @@ #include <mainboard/gpio.h> #include <soc/ramstage.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/mainboard/system76/bonw14/ramstage.c b/src/mainboard/system76/bonw14/ramstage.c index 839b84a..43ee54f 100644 --- a/src/mainboard/system76/bonw14/ramstage.c +++ b/src/mainboard/system76/bonw14/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <mainboard/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/cml-u/ramstage.c b/src/mainboard/system76/cml-u/ramstage.c index 839b84a..43ee54f 100644 --- a/src/mainboard/system76/cml-u/ramstage.c +++ b/src/mainboard/system76/cml-u/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <mainboard/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/gaze15/ramstage.c b/src/mainboard/system76/gaze15/ramstage.c index 376849f..ca6f64b1 100644 --- a/src/mainboard/system76/gaze15/ramstage.c +++ b/src/mainboard/system76/gaze15/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <variant/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/oryp5/ramstage.c b/src/mainboard/system76/oryp5/ramstage.c index 839b84a..43ee54f 100644 --- a/src/mainboard/system76/oryp5/ramstage.c +++ b/src/mainboard/system76/oryp5/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <mainboard/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/oryp6/ramstage.c b/src/mainboard/system76/oryp6/ramstage.c index 376849f..ca6f64b1 100644 --- a/src/mainboard/system76/oryp6/ramstage.c +++ b/src/mainboard/system76/oryp6/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <variant/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/tgl-h/ramstage.c b/src/mainboard/system76/tgl-h/ramstage.c index 49b9934..480c49c 100644 --- a/src/mainboard/system76/tgl-h/ramstage.c +++ b/src/mainboard/system76/tgl-h/ramstage.c @@ -2,12 +2,6 @@ #include <soc/ramstage.h> #include <variant/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/tgl-u/ramstage.c b/src/mainboard/system76/tgl-u/ramstage.c index a01391a..a3b12bb 100644 --- a/src/mainboard/system76/tgl-u/ramstage.c +++ b/src/mainboard/system76/tgl-u/ramstage.c @@ -2,12 +2,6 @@ #include <mainboard/gpio.h> #include <soc/ramstage.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c index 839b84a..43ee54f 100644 --- a/src/mainboard/system76/whl-u/ramstage.c +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -2,12 +2,6 @@ #include <device/device.h> #include <mainboard/gpio.h> -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} static void mainboard_init(void *chip_info) { -- To view, visit https://review.coreboot.org/c/coreboot/+/71802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Gerrit-Change-Number: 71802 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/google/brya: remove the skolas baseboard
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73388 ) Change subject: mb/google/brya: remove the skolas baseboard ...................................................................... mb/google/brya: remove the skolas baseboard The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc D src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb D src/mainboard/google/brya/variants/baseboard/skolas/gpio.c D src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h D src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h D src/mainboard/google/brya/variants/baseboard/skolas/memory.c D src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c 9 files changed, 29 insertions(+), 898 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b3e804c..b0bdfc4 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -89,18 +89,6 @@ select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE -config BOARD_GOOGLE_BASEBOARD_SKOLAS - def_bool n - select BOARD_GOOGLE_BRYA_COMMON - select BOARD_ROMSIZE_KB_32768 - select HAVE_SLP_S0_GATE - select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE - select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - select SOC_INTEL_RAPTORLAKE - select SYSTEM_TYPE_LAPTOP - select TPM_GOOGLE_CR50 - if BOARD_GOOGLE_BRYA_COMMON config BASEBOARD_DIR @@ -109,7 +97,6 @@ default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK default "hades" if BOARD_GOOGLE_BASEBOARD_HADES default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA - default "skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -199,7 +186,6 @@ default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK default "Google_Hades" if BOARD_GOOGLE_BASEBOARD_HADES default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA - default "Google_Skolas" if BOARD_GOOGLE_BASEBOARD_SKOLAS config MAINBOARD_PART_NUMBER default "Brya" if BOARD_GOOGLE_BRYA0 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 71b36ac..f63efdf 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -142,7 +142,8 @@ config BOARD_GOOGLE_SKOLAS bool "-> Skolas" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_SX9324 @@ -151,7 +152,8 @@ config BOARD_GOOGLE_SKOLAS4ES bool "-> Skolas4ES" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DEFAULT_ADL_NEM select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA @@ -303,7 +305,8 @@ config BOARD_GOOGLE_ZYDRON bool "-> Zydron" - select BOARD_GOOGLE_BASEBOARD_SKOLAS + select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DEFAULT_ADL_NEM select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_NAU8825 diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc deleted file mode 100644 index 8a4b2ac..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -bootblock-y += gpio.c - -romstage-y += memory.c -romstage-y += gpio.c - -ramstage-y += gpio.c -ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb deleted file mode 100644 index 70e7779..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ /dev/null @@ -1,171 +0,0 @@ -chip soc/intel/alderlake - - # GPE configuration - register "pmc_gpe0_dw0" = "GPP_A" - register "pmc_gpe0_dw1" = "GPP_E" - register "pmc_gpe0_dw2" = "GPP_F" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - # S0ix enable - register "s0ix_enable" = "1" - - # DPTF enable - register "dptf_enable" = "1" - - register "tcc_offset" = "10" # TCC of 90 - - # Enable CNVi BT - register "cnvi_bt_core" = "true" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" - register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" - - register "serial_io_i2c_mode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "serial_io_gspi_mode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" - register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" - register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" - register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" - register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" - - # HD Audio - register "pch_hda_dsp_enable" = "1" - register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" - register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" - register "pch_hda_idisp_codec_enable" = "1" - - # FIVR RFI Spread Spectrum 1.5% - register "fivr_spread_spectrum" = "FIVR_SS_1_5" - - # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio and WFC | - #| I2C1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C2 | SAR0 | - #| I2C3 | Touchscreen | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 900, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 600, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, - }, - }" - - device domain 0 on - device ref igpu on end - device ref dtt on end - device ref tbt_pcie_rp0 on end - device ref tbt_pcie_rp1 on end - device ref tbt_pcie_rp2 on end - device ref tcss_xhci on end - device ref tcss_dma0 on end - device ref tcss_dma1 on end - device ref xhci on end - device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - register "add_acpi_dma_property" = "true" - device generic 0 on end - end - end - device ref i2c3 on end - device ref heci1 on end - device ref sata on end - device ref pcie_rp8 on - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card - device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 1 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE9-12 SSD - device ref uart0 on end - device ref gspi1 on end - device ref pch_espi on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device ref hda on end - end -end diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c b/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c deleted file mode 100644 index cd0be69..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/gpio.c +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <types.h> -#include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ - /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ - /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ - /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ - /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ - /* A4 : ESPI_CS# ==> ESPI_CS_L */ - /* A5 : ESPI_ALERT0# ==> NC */ - PAD_NC(GPP_A5, NONE), - /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ - PAD_CFG_GPI(GPP_A6, NONE, DEEP), - /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), - /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* A9 : ESPI_CLK ==> ESPI_CLK */ - /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ - /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), - /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ - PAD_CFG_GPO(GPP_A17, 1, DEEP), - /* A18 : DDSP_HPDB ==> HDMI_HPD */ - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6), - /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6), - /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), - /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), - /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), - - /* B0 : SOC_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* B1 : SOC_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> M2_SSD_PLA_L */ - PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG), - /* B3 : PROC_GP2 ==> SAR2_INT_L */ - PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), - /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), - /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), - /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), - /* B9 : NC */ - PAD_NC(GPP_B9, NONE), - /* B10 : NC */ - PAD_NC(GPP_B10, NONE), - /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* B12 : SLP_S0# ==> SLP_S0_L */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* B13 : PLTRST# ==> PLT_RST_L */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), - /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */ - PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG), - /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ - PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), - /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ - PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), - /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ - PAD_NC(GPP_B18, NONE), - /* B19 : NC */ - PAD_NC(GPP_B19, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ - PAD_NC(GPP_B23, NONE), - - /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - /* C2 : SMBALERT# ==> GPP_C2_STRAP */ - PAD_NC(GPP_C2, NONE), - /* C3 : SML0CLK ==> EN_UCAM_PWR */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), - /* C4 : SML0DATA ==> EN_UCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_C4, 0, DEEP), - /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ - PAD_NC(GPP_C5, NONE), - /* C6 : SML1CLK ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_C6, 0, DEEP), - /* C7 : SML1DATA ==> USI_INT */ - PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), - - /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), - /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), - /* D3 : ISH_GP3 ==> WCAM_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), - /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ - PAD_CFG_GPO(GPP_D5, 1, DEEP), - /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), - /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), - /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */ - PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG), - /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */ - PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG), - /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), - /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), - /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), - /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), - /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - - /* E0 : see end of E group */ - /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), - /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), - /* E3 : PROC_GP0 ==> HPS_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), - /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_E4, 0, DEEP), - /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ - PAD_CFG_GPO(GPP_E5, 1, DEEP), - /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), - /* E7 : PROC_GP1 ==> EN_HPS_PWR */ - PAD_CFG_GPO(GPP_E7, 1, DEEP), - /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ - PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), - /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ - PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG), - /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ - PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), - /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), - /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* E16 : RSVD_TP ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_E16, 1, DEEP), - /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ - PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), - /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), - /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), - /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), - /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L - NB. Driven high here so that it is sequenced after WWAN_RST_L; a - PERST# signal would normally be reset by PLRST#, but here it will be - explicitly programmed during a power-down sequence. */ - PAD_CFG_GPO(GPP_E0, 1, DEEP), - - /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ - PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), - /* F7 : GPPF7_STRAP */ - PAD_NC(GPP_F7, NONE), - /* F8 : NC */ - PAD_NC(GPP_F8, NONE), - /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - /* F10 : GPPF10_STRAP */ - PAD_NC(GPP_F10, DN_20K), - /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), - /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), - /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), - /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT), - /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), - /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), - /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ - PAD_CFG_GPO(GPP_F19, 1, PLTRST), - /* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* F23 : NC */ - PAD_NC(GPP_F23, NONE), - - /* H0 : GPPH0_BOOT_STRAP1 */ - PAD_NC(GPP_H0, NONE), - /* H1 : GPPH1_BOOT_STRAP2 */ - PAD_NC(GPP_H1, NONE), - /* H2 : GPPH2_BOOT_STRAP3 */ - PAD_NC(GPP_H2, NONE), - /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), - /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), - /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG), - /* H14 : NC */ - PAD_NC(GPP_H14, NONE), - /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), - /* H16 : NC */ - PAD_NC(GPP_H16, NONE), - /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), - /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H20, 1, DEEP), - /* H21 : IMGCLKOUT2 ==> UCAM_MCLK */ - PAD_CFG_GPO(GPP_H21, 0, DEEP), - /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), - - /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), - /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), - /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - - /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), - /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), - /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), - /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), - /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - - /* GPD0: BATLOW# ==> BATLOW_L */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4: SLP_S3# ==> SLP_S3_L */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5: SLP_S4# ==> SLP_S4_L */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6: SLP_A# ==> SLP_A_L */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7: GPD7_STRAP */ - PAD_NC(GPD7, NONE), - /* GPD8: SUSCLK ==> PCH_SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10: SLP_S5# ==> SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ - PAD_CFG_GPI(GPD11, NONE, DEEP), - - /* Virtual GPIO */ - /* Put unused Cnvi BT UART lines in NC mode since we use USB mode. */ - PAD_NC(GPP_VGPIO_6, NONE), - PAD_NC(GPP_VGPIO_7, NONE), - PAD_NC(GPP_VGPIO_8, NONE), - PAD_NC(GPP_VGPIO_9, NONE), - - /* Put unused Cnvi UART0 lines in NC mode since we use USB mode. */ - PAD_NC(GPP_VGPIO_18, NONE), - PAD_NC(GPP_VGPIO_19, NONE), - PAD_NC(GPP_VGPIO_20, NONE), - PAD_NC(GPP_VGPIO_21, NONE), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L - * To meet timing constrains - drive reset low. - * Deasserted in ramstage. - */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), -}; - -const struct pad_config *__weak variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *__weak variant_gpio_override_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *__weak variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), -}; - -DECLARE_WEAK_CROS_GPIOS(cros_gpios); - -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) -{ - *num = 0; - return NULL; -} diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h deleted file mode 100644 index ef156f1..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* - * EC can wake from S3/S0ix with: - * 1. Lid open - * 2. AC Connect/Disconnect - * 3. Power button - * 4. Key press - * 5. Mode change - * 6. Low battery - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) -/* - * ACPI related definitions for ASL code. - */ -/* Enable Keyboard Backlight */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT -/* Enable MKBP for buttons and switches */ -#define EC_ENABLE_MKBP_DEVICE -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h deleted file mode 100644 index 0de7ffd..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/gpio.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI -/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ -#define GPE_EC_WAKE GPE0_DW2_17 -/* WP signal to PCH */ -#define GPIO_PCH_WP GPP_E15 -/* EC in RW or RO */ -#define GPIO_EC_IN_RW GPP_F18 -/* Used to gate SoC's SLP_S0# signal */ -#define GPIO_SLP_S0_GATE GPP_F9 -/* GPIO IRQ for tight timestamps / wake support */ -#define EC_SYNC_IRQ GPP_F17_IRQ - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/memory.c b/src/mainboard/google/brya/variants/baseboard/skolas/memory.c deleted file mode 100644 index bcad9b4..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/memory.c +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <gpio.h> - -static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP4X, - - .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .resistor = 100, - - /* Baseboard Rcomp target values */ - .targets = {40, 30, 30, 30, 30}, - }, - - /* DQ byte map */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, - .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, - }, - .ddr1 = { - .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, - .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, - }, - .ddr2 = { - .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, - .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, - }, - .ddr3 = { - .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, - .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, - }, - .ddr4 = { - .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, - .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, - }, - .ddr5 = { - .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, - .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, - }, - .ddr6 = { - .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, - .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, - }, - .ddr7 = { - .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, - .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, - }, - }, - - /* DQS CPU<>DRAM map */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, - }, - - .ect = 1, /* Enable Early Command Training */ -}; - -const struct mb_cfg *__weak variant_memory_params(void) -{ - return &baseboard_memcfg; -} - -int __weak variant_memory_sku(void) -{ - /* - * Memory configuration board straps - * GPIO_MEM_CONFIG_0 GPP_E11 - * GPIO_MEM_CONFIG_1 GPP_E2 - * GPIO_MEM_CONFIG_2 GPP_E1 - * GPIO_MEM_CONFIG_3 GPP_E12 - */ - gpio_t spd_gpios[] = { - GPP_E11, - GPP_E2, - GPP_E1, - GPP_E12, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - -bool __weak variant_is_half_populated(void) -{ - /* GPIO_MEM_CH_SEL GPP_E13 */ - return gpio_get(GPP_E13); -} - -void __weak variant_get_spd_info(struct mem_spd *spd_info) -{ - spd_info->topo = MEM_TOPO_MEMORY_DOWN; - spd_info->cbfs_index = variant_memory_sku(); -} diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c b/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c deleted file mode 100644 index 9c2d4aa..0000000 --- a/src/mainboard/google/brya/variants/baseboard/skolas/ramstage.c +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <acpi/acpi_device.h> -#include <baseboard/variants.h> -#include <console/console.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> - -#include <drivers/intel/dptf/chip.h> -#include <intelblocks/power_limit.h> - -WEAK_DEV_PTR(dptf_policy); - -void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) -{ - if (!num_entries) - return; - - const struct device *policy_dev = DEV_PTR(dptf_policy); - if (!policy_dev) - return; - - struct drivers_intel_dptf_config *config = policy_dev->chip_info; - - uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); - - u8 tdp = get_cpu_tdp(); - - for (size_t i = 0; i < num_entries; i++) { - if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { - struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; - settings->pl1.min_power = limits[i].pl1_min_power; - settings->pl1.max_power = limits[i].pl1_max_power; - settings->pl2.min_power = limits[i].pl2_min_power; - settings->pl2.max_power = limits[i].pl2_max_power; - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); - printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", - limits[i].pl1_min_power, - limits[i].pl1_max_power, - limits[i].pl2_min_power, - limits[i].pl2_max_power, - limits[i].pl4_power); - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/73388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Gerrit-Change-Number: 73388 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/picasso/acpi: factor out get_cstate_info functionality
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/73425 ) Change subject: soc/amd/picasso/acpi: factor out get_cstate_info functionality ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/73425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8200bb9a0ccacd3c1020cee58f866d2f11671070 Gerrit-Change-Number: 73425 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: only use constants in cstate_info
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/73424 ) Change subject: soc/amd/picasso/acpi: only use constants in cstate_info ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/73424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202047a6632cd13e81ac3c93f5e108e269c2ce03 Gerrit-Change-Number: 73424 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/skyrim: Disable cardbus support
by Karthik Ramasubramanian (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Martin L Roth, Martin Roth, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73167 ) Change subject: mb/google/skyrim: Disable cardbus support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Gerrit-Change-Number: 73167 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Mar 2023 00:24:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/skyrim: override winterhold & whiterun PCIe config
by Martin L Roth (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Nien, Martin Roth. Hello Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73441 to look at the new patch set (#2). Change subject: mb/google/skyrim: override winterhold & whiterun PCIe config ...................................................................... mb/google/skyrim: override winterhold & whiterun PCIe config Winterhold & Whiterun boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d --- M src/mainboard/google/skyrim/variants/whiterun/Makefile.inc A src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.inc A src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 4 files changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/73441/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Gerrit-Change-Number: 73441 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/skyrim: override winterhold & whiterun pcie config
by Martin L Roth (Code Review) 03 Mar '23

03 Mar '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73441 ) Change subject: mb/google/skyrim: override winterhold & whiterun pcie config ...................................................................... mb/google/skyrim: override winterhold & whiterun pcie config Winterhold & Whiterun boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d --- M src/mainboard/google/skyrim/variants/whiterun/Makefile.inc A src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.inc A src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 4 files changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/73441/1 diff --git a/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc index db72b15..26b1ce2 100644 --- a/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/whiterun/Makefile.inc @@ -2,4 +2,7 @@ subdirs-y += ./memory +romstage-y += port_descriptors.c + ramstage-y += gpio.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c b/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c new file mode 100644 index 0000000..9e55a6f --- /dev/null +++ b/src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor emmc_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* eMMC */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { + /* SSD is disabled */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 2, + .end_logical_lane = 3, + .turn_off_unused_lanes = true, + }, +}; + +static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* eMMC is disabled */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 1, + .end_logical_lane = 1, + .turn_off_unused_lanes = true, + }, + { + /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_6, + .clk_req = CLK_REQ0, + }, +}; + +#define NVME_CLKREQ_GPIO 92 +void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) +{ + /* + * We can determine if a device is populated based on the state of the clkreq + * signal. If the device is present, the clkreq is held low by the device. If + * no device is present, clkreq is pulled high by an external pull-up. + * + * This allows checking the state of the NVMe device clkreq signal and enabling + * either eMMC or NVMe based on that. + */ + if (gpio_get(NVME_CLKREQ_GPIO)) { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling NVMe.\n"); + *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); + *dxio_descs = nvme_dxio_descriptors; + } +} diff --git a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc index db72b15..26b1ce2 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/winterhold/Makefile.inc @@ -2,4 +2,7 @@ subdirs-y += ./memory +romstage-y += port_descriptors.c + ramstage-y += gpio.c +ramstage-y += port_descriptors.c diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c new file mode 100644 index 0000000..9e55a6f --- /dev/null +++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +static const fsp_dxio_descriptor emmc_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* eMMC */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { + /* SSD is disabled */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 2, + .end_logical_lane = 3, + .turn_off_unused_lanes = true, + }, +}; + +static const fsp_dxio_descriptor nvme_dxio_descriptors[] = { + { + /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .clk_req = CLK_REQ2, + }, + { + /* eMMC is disabled */ + .engine_type = UNUSED_ENGINE, + .port_present = false, + .start_logical_lane = 1, + .end_logical_lane = 1, + .turn_off_unused_lanes = true, + }, + { + /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .gpio_group_id = GPIO_6, + .clk_req = CLK_REQ0, + }, +}; + +#define NVME_CLKREQ_GPIO 92 +void variant_get_dxio_descriptor(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num) +{ + /* + * We can determine if a device is populated based on the state of the clkreq + * signal. If the device is present, the clkreq is held low by the device. If + * no device is present, clkreq is pulled high by an external pull-up. + * + * This allows checking the state of the NVMe device clkreq signal and enabling + * either eMMC or NVMe based on that. + */ + if (gpio_get(NVME_CLKREQ_GPIO)) { + printk(BIOS_DEBUG, "Enabling eMMC.\n"); + *dxio_num = ARRAY_SIZE(emmc_dxio_descriptors); + *dxio_descs = emmc_dxio_descriptors; + } else { + printk(BIOS_DEBUG, "Enabling NVMe.\n"); + *dxio_num = ARRAY_SIZE(nvme_dxio_descriptors); + *dxio_descs = nvme_dxio_descriptors; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Gerrit-Change-Number: 73441 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by Karthik Ramasubramanian (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Frank Wu, John Su, Jason Nien, Eric Lai, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73252 ) Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Gerrit-Change-Number: 73252 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sat, 04 Mar 2023 00:17:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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