coreboot-gerrit March 2023

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[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed
by Eric Lai (Code Review) 03 Mar '23

03 Mar '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73251 ) Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed ...................................................................... spd/lp5: Modify Hynix LPDDR5X memory Speed Because SPD tool now supports 8533Mbps, so modify speed to regenerate the SPD file for Hynix H58G66BK8BX067 and H58G56BK8BX068. BUG=b:263189532, b:270629852 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73251 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt A spd/lp5/set-0/spd-10.hex A spd/lp5/set-0/spd-11.hex M spd/lp5/set-1/parts_spd_manifest.generated.txt A spd/lp5/set-1/spd-10.hex A spd/lp5/set-1/spd-11.hex 7 files changed, 157 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Ian Feng: Looks good to me, approved Eric Lai: Looks good to me, approved Chao Gui: Looks good to me, but someone else must approve diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index 2332459..fc2e120 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -204,7 +204,7 @@ "diesPerPackage": 4, "bitWidthPerChannel": 16, "ranksPerChannel": 2, - "speedMbps": 7500, + "speedMbps": 8533, "lp5x": true } }, @@ -215,7 +215,7 @@ "diesPerPackage": 2, "bitWidthPerChannel": 16, "ranksPerChannel": 1, - "speedMbps": 7500, + "speedMbps": 8533, "lp5x": true } } diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index d9a3d6b..9e8e241 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -20,5 +20,5 @@ H58G66BK7BX067,spd-8.hex H58G56BK7BX068,spd-7.hex H9JCNNNFA5MLYR-N6E,spd-4.hex -H58G66BK8BX067,spd-8.hex -H58G56BK8BX068,spd-7.hex +H58G66BK8BX067,spd-10.hex +H58G56BK8BX068,spd-11.hex diff --git a/spd/lp5/set-0/spd-10.hex b/spd/lp5/set-0/spd-10.hex new file mode 100644 index 0000000..746728e --- /dev/null +++ b/spd/lp5/set-0/spd-10.hex @@ -0,0 +1,32 @@ +23 10 15 0E 16 22 B5 08 00 00 00 00 0A 01 00 00 +00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-0/spd-11.hex b/spd/lp5/set-0/spd-11.hex new file mode 100644 index 0000000..b2e92a6 --- /dev/null +++ b/spd/lp5/set-0/spd-11.hex @@ -0,0 +1,32 @@ +23 10 15 0E 16 22 95 08 00 00 00 00 02 01 00 00 +00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt index d9a3d6b..9e8e241 100644 --- a/spd/lp5/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -20,5 +20,5 @@ H58G66BK7BX067,spd-8.hex H58G56BK7BX068,spd-7.hex H9JCNNNFA5MLYR-N6E,spd-4.hex -H58G66BK8BX067,spd-8.hex -H58G56BK8BX068,spd-7.hex +H58G66BK8BX067,spd-10.hex +H58G56BK8BX068,spd-11.hex diff --git a/spd/lp5/set-1/spd-10.hex b/spd/lp5/set-1/spd-10.hex new file mode 100644 index 0000000..d51bbc9 --- /dev/null +++ b/spd/lp5/set-1/spd-10.hex @@ -0,0 +1,32 @@ +23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00 +00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-11.hex b/spd/lp5/set-1/spd-11.hex new file mode 100644 index 0000000..40383fb --- /dev/null +++ b/spd/lp5/set-1/spd-11.hex @@ -0,0 +1,32 @@ +23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00 +00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/73251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Gerrit-Change-Number: 73251 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73443 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... mb/google/geralt:set tps65132s program eeprom For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V,so write the default value in eeprom to +-5.7V when configure display for the first time. In this way,the default voltage is +-5.7V when you start or enter the kernel next time. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/display.c M src/mainboard/google/geralt/panel_geralt.c 2 files changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/73443/1 diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 396d6e0..0e153bd 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -3,6 +3,7 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <device/i2c_simple.h> #include <edid.h> #include <framebuffer_info.h> #include <gpio.h> @@ -10,11 +11,54 @@ #include <soc/dptx.h> #include <soc/dsi.h> #include <soc/gpio_common.h> +#include <soc/i2c.h> #include <soc/mtcmos.h> #include "display.h" +#include "gpio.h" #include "panel.h" +#define PMIC_TPS65132_I2C I2C3 +#define PMIC_TPS65132_SLAVE 0x3E + +static void tps65132s_program_eeprom(void) +{ + u8 value = 0; + u8 value1 = 0; + + /* Initialize I2C3 for PMIC TPS65132 */ + mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); + mdelay(10); + + gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); + gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); + mdelay(10); + + i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, &value, 0xFF, 0); + i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, &value1, 0xFF, 0); + + if (!(value == 0x11 && value1 == 0x11)) { + + printk(BIOS_INFO, "Just set AVDD AVEE 5.7V to EEPROM Data in first time.\n"); + /* Set AVDD = 5.7V */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x11, 0x1F) < 0) + return; + + /* Set AVEE = -5.7V */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x11, 0x1F) < 0) + return; + + /* Set EEPROM Data */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0xFF, 0x80, 0xFC) < 0) + return; + mdelay(50); + } + + gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 0); + gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 0); + mdelay(5); +} + int configure_display(void) { struct edid edid; @@ -26,6 +70,7 @@ printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); + tps65132s_program_eeprom(); mtcmos_display_power_on(); panel->configure_panel_backlight(); diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 2991360..60c1f5f5 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -14,8 +14,6 @@ #include "gpio.h" #include "panel.h" -#define PMIC_TPS65132_I2C I2C3 -#define PMIC_TPS65132_SLAVE 0x3E static void configure_mipi_pwm_backlight(void) { @@ -33,25 +31,12 @@ /* Enable VM18V */ mainboard_enable_regulator(MTK_REGULATOR_VDD18, true); - /* Initialize I2C3 for PMIC TPS65132 */ - mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); - mdelay(10); - gpio_output(GPIO_DISP_RST_1V8_L, 0); mdelay(1); gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); mdelay(10); - - /* Set AVDD = 5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x11, 0x1F) < 0) - return; - - /* Set AVEE = -5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x11, 0x1F) < 0) - return; - gpio_output(GPIO_DISP_RST_1V8_L, 1); mdelay(1); gpio_output(GPIO_DISP_RST_1V8_L, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/73443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73443 Gerrit-PatchSet: 1 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73442/comment/af7ed4cd_51ab9bd4 PS1, Line 10: so write the default value in eeprom to +-5.7V when configure display for the first time. > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 3 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Mar 2023 02:58:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... Patch Set 3: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73442/comment/99579af9_03dc2774 PS1, Line 8: > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. https://review.coreboot.org/c/coreboot/+/73442/comment/7fbc707a_d207a052 PS1, Line 9: For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V, > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. https://review.coreboot.org/c/coreboot/+/73442/comment/1f3e9497_5cbf134d PS1, Line 13: BUG=b:268292556 > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 3 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Mar 2023 02:56:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... mb/google/geralt:set tps65132s program eeprom For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V,so write the default value in eeprom to +-5.7V when configure display for the first time.In this way,the default voltage is +-5.7V when you start or enter the kernel next time. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/display.c M src/mainboard/google/geralt/panel_geralt.c 2 files changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/73442/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 3 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... mb/google/geralt:set tps65132s program eeprom For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V,so write the default value in eeprom to +-5.7V when configure display for the first time.In this way,the default voltage is +-5.7V when you start or enter the kernel next time. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/display.c M src/mainboard/google/geralt/panel_geralt.c 2 files changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/73442/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 2 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by build bot (Jenkins) (Code Review) 03 Mar '23

03 Mar '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... Patch Set 1: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171430): https://review.coreboot.org/c/coreboot/+/73442/comment/f32860cb_5b3d5b92 PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171430): https://review.coreboot.org/c/coreboot/+/73442/comment/febce8a3_9a889ab0 PS1, Line 9: For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171430): https://review.coreboot.org/c/coreboot/+/73442/comment/e2a28b61_11fd63f0 PS1, Line 10: so write the default value in eeprom to +-5.7V when configure display for the first time. Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171430): https://review.coreboot.org/c/coreboot/+/73442/comment/6a416794_992ec03a PS1, Line 13: BUG=b:268292556 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 1 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Mar 2023 02:42:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/geralt:set tps65132s program eeprom
by yangcong (Code Review) 03 Mar '23

03 Mar '23

yangcong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73442 ) Change subject: mb/google/geralt:set tps65132s program eeprom ...................................................................... mb/google/geralt:set tps65132s program eeprom For Geralt,it is necessary to increase the AVDD/AVEE of TPS65132S PMIC to +-5.7V, so write the default value in eeprom to +-5.7V when configure display for the first time. In this way,the default voltage is +-5.7V when you start or enter the kernel next time. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V for BOE_TV110C9M_LL0 on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/geralt/display.c M src/mainboard/google/geralt/panel_geralt.c 2 files changed, 62 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/73442/1 diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 396d6e0..0e153bd 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -3,6 +3,7 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <device/i2c_simple.h> #include <edid.h> #include <framebuffer_info.h> #include <gpio.h> @@ -10,11 +11,54 @@ #include <soc/dptx.h> #include <soc/dsi.h> #include <soc/gpio_common.h> +#include <soc/i2c.h> #include <soc/mtcmos.h> #include "display.h" +#include "gpio.h" #include "panel.h" +#define PMIC_TPS65132_I2C I2C3 +#define PMIC_TPS65132_SLAVE 0x3E + +static void tps65132s_program_eeprom(void) +{ + u8 value = 0; + u8 value1 = 0; + + /* Initialize I2C3 for PMIC TPS65132 */ + mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); + mdelay(10); + + gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); + gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); + mdelay(10); + + i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, &value, 0xFF, 0); + i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, &value1, 0xFF, 0); + + if (!(value == 0x11 && value1 == 0x11)) { + + printk(BIOS_INFO, "Just set AVDD AVEE 5.7V to EEPROM Data in first time.\n"); + /* Set AVDD = 5.7V */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x11, 0x1F) < 0) + return; + + /* Set AVEE = -5.7V */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x11, 0x1F) < 0) + return; + + /* Set EEPROM Data */ + if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0xFF, 0x80, 0xFC) < 0) + return; + mdelay(50); + } + + gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 0); + gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 0); + mdelay(5); +} + int configure_display(void) { struct edid edid; @@ -26,6 +70,7 @@ printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); + tps65132s_program_eeprom(); mtcmos_display_power_on(); panel->configure_panel_backlight(); diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 2991360..60c1f5f5 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -14,8 +14,6 @@ #include "gpio.h" #include "panel.h" -#define PMIC_TPS65132_I2C I2C3 -#define PMIC_TPS65132_SLAVE 0x3E static void configure_mipi_pwm_backlight(void) { @@ -33,25 +31,12 @@ /* Enable VM18V */ mainboard_enable_regulator(MTK_REGULATOR_VDD18, true); - /* Initialize I2C3 for PMIC TPS65132 */ - mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); - mdelay(10); - gpio_output(GPIO_DISP_RST_1V8_L, 0); mdelay(1); gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); mdelay(10); - - /* Set AVDD = 5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x11, 0x1F) < 0) - return; - - /* Set AVEE = -5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x11, 0x1F) < 0) - return; - gpio_output(GPIO_DISP_RST_1V8_L, 1); mdelay(1); gpio_output(GPIO_DISP_RST_1V8_L, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/73442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73442 Gerrit-PatchSet: 1 Gerrit-Owner: yangcong <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Update DPTC and STT settings
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73081 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/skyrim/var/frostflow: Update DPTC and STT settings ...................................................................... mb/google/skyrim/var/frostflow: Update DPTC and STT settings According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: John Su <john_su(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified John Su: Looks good to me, approved Tim Van Patten: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index b34e2e3..86b1c94 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -147,4 +147,27 @@ end end # UART1 + # Set Package Power Parameters + register "thermctl_limit_degreeC" = "90" + + # STT settings + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0x2666" + register "stt_min_limit" = "15000" + register "stt_skin_temp_apu" = "0x3000" + + # STT default mode + register "stt_m1" = "0xfed2" + register "stt_m2" = "0x5f9" + register "stt_c_apu" = "0xfbf8" + register "stt_alpha_apu" = "0x4ccd" + + # STT tablet mode + register "stt_m1_tablet" = "0x208" + register "stt_m2_tablet" = "0x1f5" + register "stt_c_apu_tablet" = "0xa2" + register "stt_alpha_apu_tablet" = "0x199a" + end # chip soc/amd/mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/73081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Gerrit-Change-Number: 73081 Gerrit-PatchSet: 10 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: Add STT support for dptc tablet mode
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73205 ) Change subject: soc/amd/mendocino: Add STT support for dptc tablet mode ...................................................................... soc/amd/mendocino: Add STT support for dptc tablet mode Add stt settings for dptc tablet mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the clamshell/tablet mode. Run the WebGL aquarium with 5000 fish and verify that there is no power drop peak. Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73205 Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/soc/amd/mendocino/chip.h M src/soc/amd/mendocino/root_complex.c 2 files changed, 30 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index dc147f8..42f27cb 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -73,6 +73,10 @@ uint32_t vrm_soc_current_limit_throttle_mA; /* tablet mode.*/ + uint16_t stt_m1_tablet; + uint16_t stt_m2_tablet; + uint16_t stt_c_apu_tablet; + uint16_t stt_alpha_apu_tablet; /* Thermal profile B*/ uint32_t fast_ppt_limit_mW_B; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index dce9498..6217246 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -264,10 +264,10 @@ config->vrm_maximum_current_limit_mA, config->vrm_soc_current_limit_mA, config->stt_min_limit, - config->stt_m1, - config->stt_m2, - config->stt_c_apu, - config->stt_alpha_apu, + config->stt_m1_tablet, + config->stt_m2_tablet, + config->stt_c_apu_tablet, + config->stt_alpha_apu_tablet, config->stt_skin_temp_apu); acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/73205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Gerrit-Change-Number: 73205 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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