coreboot-gerrit March 2023

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[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed
by Karthik Ramasubramanian (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: John Su, Tarun Tuli, Subrata Banik, Nick Vaccaro, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 ) Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Gerrit-Change-Number: 73251 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sat, 04 Mar 2023 00:16:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITX
by Kevin Keijzer (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans, Nicholas Chin, Fabian Groffen, Elyes Haouas. Kevin Keijzer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73097 ) Change subject: mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITX ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: Hardware monitoring wasn't working from Linux. When trying to load the `nct6775` module, it would fail, saying "Refusing to enable a Super-I/O device with a base I/O port 0". This is because the device wasn't enabled in devicetree.cb. I've found the fix and tested it, and now the `sensors` command shows all the outputs for the `nct6776-isa-0290` ISA adapter. File src/mainboard/asrock/b75m-itx/devicetree.cb: https://review.coreboot.org/c/coreboot/+/73097/comment/b8cb77cc_204c6892 PS3, Line 122: device pnp 2e.b off end # HWM, front panel Change this as follows to enable hardware monitoring from Linux: ``` device pnp 2e.b on # HWM, front panel LED irq 0x30 = 0xe1 # + Fan RPM sense pins io 0x60 = 0x0290 # + HWM base address end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/73097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6a6eb3e922920f4afbcb7828cd2b779b9caebcb Gerrit-Change-Number: 73097 Gerrit-PatchSet: 3 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kevin Keijzer Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 03 Mar 2023 23:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Disable cardbus support
by Matt DeVillier (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Martin L Roth, Martin Roth, Karthik Ramasubramanian, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73167 ) Change subject: mb/google/skyrim: Disable cardbus support ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73167/comment/d60cdfd1_d01691f4 PS1, Line 11: Maybe cardbus support shouldn't be enabled by default? agreed -- To view, visit https://review.coreboot.org/c/coreboot/+/73167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Gerrit-Change-Number: 73167 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 23:11:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up ucode for RPL-P/H/U
by Felix Singer (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tim Crawford, Tarun Tuli, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73436 ) Change subject: soc/intel/alderlake: Hook up ucode for RPL-P/H/U ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Gerrit-Change-Number: 73436 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 23:08:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Disable cardbus support
by Jason Glenesk (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Martin Roth, Karthik Ramasubramanian, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73167 ) Change subject: mb/google/skyrim: Disable cardbus support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Gerrit-Change-Number: 73167 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 23:03:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed
by Chao Gui (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: John Su, Tarun Tuli, Subrata Banik, Nick Vaccaro, Martin Roth. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 ) Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813fc1495836dbe33de426cf41a1f58c8e8a046e Gerrit-Change-Number: 73251 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 22:12:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73387 ) Change subject: soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation ...................................................................... soc/amd/cezanne/graphics: simplify map_oprom_vendev implementation Phoenix' implementation of map_oprom_vendev uses this simplified implementation, so port this back to Cezanne too. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73387 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/graphics.c 1 file changed, 18 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/graphics.c b/src/soc/amd/cezanne/graphics.c index 491ca87..2a06443 100644 --- a/src/soc/amd/cezanne/graphics.c +++ b/src/soc/amd/cezanne/graphics.c @@ -6,14 +6,11 @@ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev = vendev; - switch (vendev) { case CEZANNE_VBIOS_VID_DID: case BARCELO_VBIOS_VID_DID: - new_vendev = CEZANNE_VBIOS_VID_DID; - break; + return CEZANNE_VBIOS_VID_DID; } - return new_vendev; + return vendev; } -- To view, visit https://review.coreboot.org/c/coreboot/+/73387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Gerrit-Change-Number: 73387 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73427 ) Change subject: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs ...................................................................... soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs The legacy ACPI CPU control registers in IO space where the first 4 IO locations control the CPU throttling value don't exist any more on the Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS in set_cstate_io_addr which will cause accesses from the 8 IO addresses beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads from those IO addresses will cause the CPU to enter low C states. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b --- M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/include/soc/iomap.h M src/soc/amd/picasso/include/soc/iomap.h 6 files changed, 24 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/73427/1 diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index fc04b25..e4fe00f 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -42,7 +42,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 8fd3715..8151b96 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -24,6 +24,6 @@ msr_t cst_addr; cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; + cst_addr.lo = ACPI_CSTATE_CONTROL; wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index bb8588c..b335b3f 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -50,7 +50,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 630940bb..1e1120c 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 5a1488b..b12b48c 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c70c64e..26022ef 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -69,8 +69,8 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ -/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */ +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ +/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CSTATE_CONTROL on are trapped in CPU core */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Gerrit-Change-Number: 73427 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT
by Martin L Roth (Code Review) 03 Mar '23

03 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73393 ) Change subject: mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT ...................................................................... mb/google/skyrim: Disable USE_SELECTIVE_GOP_INIT This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 20 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 22caf51..dfc8030 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -44,7 +44,6 @@ select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI - select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select PCIEXP_ASPM @@ -118,9 +117,6 @@ default "crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT default "markarth" if BOARD_GOOGLE_MARKARTH -config USE_SELECTIVE_GOP_INIT - default y if CHROMEOS && RUN_FSP_GOP - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH -- To view, visit https://review.coreboot.org/c/coreboot/+/73393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Gerrit-Change-Number: 73393 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/variant/bb/{brya,hades}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: PS8: > skolas is being dropped. for clarity -- skolas Baseboard is dropped (skolas will become another brya variant) -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 21:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

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