coreboot-gerrit March 2023

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[S] Change in coreboot[master]: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73422 ) Change subject: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define ...................................................................... soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define Picasso and newer don't implement the P_CNT register to control the CPU duty cycle and also trap the C state control IO addresses directly in the CPU, so those won't reach the FCH. This register is unused in the Picasso code and not even defined any more in the Cezanne PPR. The Picasso PPR does define this register, but since it's useless and might even just be a leftover form a pre-Zen CPU generation, drop the define. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/73422/1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a3fb1a2..31f3ed6 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -47,7 +47,6 @@ #define TIMER_STS BIT(0) #define PM1_CNT_BLK 0x62 #define PM_TMR_BLK 0x64 -#define PM_CPU_CTRL 0x66 #define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 -- To view, visit https://review.coreboot.org/c/coreboot/+/73422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Gerrit-Change-Number: 73422 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: skyrim/overridetree.cb: Remove gpio_keys ACPI node
by Martin L Roth (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73299 ) Change subject: skyrim/overridetree.cb: Remove gpio_keys ACPI node ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5 Gerrit-Change-Number: 73299 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 17:21:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/acpi: drop unnecessary duty_offset/duty_width field writes
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73421 ) Change subject: soc/amd/*/acpi: drop unnecessary duty_offset/duty_width field writes ...................................................................... soc/amd/*/acpi: drop unnecessary duty_offset/duty_width field writes The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the duty_offset and duty_width FADT field in acpi_fill_fadt for all SoC except Stoneyridge. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib63b24891d44298841153dfc500b030619e1a5ea --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c 5 files changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/73421/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 35b3989..4ebd321 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -78,8 +78,6 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 0; /* Not supported */ - fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 7c66d54..e7dba0f 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -81,8 +81,6 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 0; /* Not supported */ - fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 03e2381..fc84f48 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -80,8 +80,6 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 0; /* Not supported */ - fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 8f6dfb5..d5f5207 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -81,8 +81,6 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 0; /* Not supported */ - fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7244a11..c5a91d7 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -86,8 +86,6 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 0; /* Not supported */ - fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib63b24891d44298841153dfc500b030619e1a5ea Gerrit-Change-Number: 73421 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: don't announce unimplemented duty cycle control
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73420 ) Change subject: soc/amd/picasso/acpi: don't announce unimplemented duty cycle control ...................................................................... soc/amd/picasso/acpi: don't announce unimplemented duty cycle control Picasso neither has the corresponding P_CNT register implemented nor writes a _PTC ACPI object that would specify the P_CNT register. The Picasso UEFI reference code also sets the duty_width FADT entry to 0. This also aligns the Picasso code with the Cezanne code in this regard. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860 --- M src/soc/amd/picasso/acpi.c 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/73420/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 89ca502..7244a11 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -86,8 +86,8 @@ overridden by the _CST packages in the processor devices. */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ - fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ + fadt->duty_offset = 0; /* Not supported */ + fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860 Gerrit-Change-Number: 73420 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/acpi: drop unneeded pstate_cnt FADT assignment
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

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[S] Change in coreboot[master]: soc/amd/*/acpi: drop unneeded mon_alrm FADT assignment
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73418 ) Change subject: soc/amd/*/acpi: drop unneeded mon_alrm FADT assignment ...................................................................... soc/amd/*/acpi: drop unneeded mon_alrm FADT assignment The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the mon_alrm FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iabb5fc7367f1e4e7acea1a58abdb643fc46ca776 --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c 6 files changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/73418/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 46eaadc..89261cf 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -83,7 +83,6 @@ fadt->duty_offset = 0; /* Not supported */ fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 675ab20..322e44e 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -86,7 +86,6 @@ fadt->duty_offset = 0; /* Not supported */ fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index fb4d103..f519917 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -85,7 +85,6 @@ fadt->duty_offset = 0; /* Not supported */ fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 25ebc66..f082518 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -86,7 +86,6 @@ fadt->duty_offset = 0; /* Not supported */ fadt->duty_width = 0; /* Not supported */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 138e743..89ca502 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -89,7 +89,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 3b45a5f..d60faaf 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -81,7 +81,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = RTC_DATE_ALARM; - fadt->mon_alrm = 0; /* Not supported */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ ACPI_FADT_C1_SUPPORTED | -- To view, visit https://review.coreboot.org/c/coreboot/+/73418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabb5fc7367f1e4e7acea1a58abdb643fc46ca776 Gerrit-Change-Number: 73418 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Keith Hui (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Felix Singer, Nico Huber, Angel Pons, Elyes Haouas. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61540 ) Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... Patch Set 7: (2 comments) Patchset: PS4: > > As far as precedents go, it has already been set. […] I just uploaded a new patch set that executes option 3. However the way Angel describes things, it may pan out more like option 4 (which isn't all that different). Elyes, I have to leave the #include in for p8z77-m(_pro) because it indirectly declares another hook for MRC raminit, that we found out the hard way earlier, as these two still supports MRC raminit. That part is being addressed by CB:72496. After we get this in, Please get that in as well, and then I'll put out a patch to completely clean those two up. Thanks. Patchset: PS7: Nico, I'm not sure if devicetree covers romstage. Even if it does, it is better done by someone better versed in devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 03 Mar 2023 17:14:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi: Add SRAT x2APIC table support
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73365 ) Change subject: acpi: Add SRAT x2APIC table support ...................................................................... acpi: Add SRAT x2APIC table support For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 04a59b1..2706bf7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -531,6 +531,19 @@ return lapic->length; } +int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic) +{ + memset((void *)x2apic, 0, sizeof(acpi_srat_x2apic_t)); + + x2apic->type = 2; /* Processor x2APIC structure */ + x2apic->length = sizeof(acpi_srat_x2apic_t); + x2apic->flags = (1 << 0); /* Enabled (the use of this structure). */ + x2apic->proximity_domain = node; + x2apic->x2apic_id = apic; + + return x2apic->length; +} + int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags) { diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index b92c77e..a108d6a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -353,6 +353,18 @@ #define ACPI_SRAT_STRUCTURE_MEM 1 #define ACPI_SRAT_STRUCTURE_GIA 5 +/* SRAT: Processor x2APIC Structure */ +typedef struct acpi_srat_x2apic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (16) */ + u16 reserved; /* Reserved - Must be zero */ + u32 proximity_domain; /* Proximity domain */ + u32 x2apic_id; /* x2APIC ID */ + u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ + u32 clock_domain; /* _CDM Clock Domain */ + u32 reserved1; /* Reserved */ +} __packed acpi_srat_x2apic_t; + /* SRAT: Processor Local APIC/SAPIC Affinity Structure */ typedef struct acpi_srat_lapic { u8 type; /* Type (0) */ @@ -1337,6 +1349,7 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint); int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); +int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/73365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Gerrit-Change-Number: 73365 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Fix CBMEM corruption
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73364 ) Change subject: soc/intel/xeon_sp: Fix CBMEM corruption ...................................................................... soc/intel/xeon_sp: Fix CBMEM corruption On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Naresh Solanki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 6ecf382..899f5ae 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -149,6 +149,7 @@ config MAX_ACPI_TABLE_SIZE_KB int + default 400 if MAX_SOCKET = 4 default 224 config FIXED_SMBUS_IO_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/73364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Gerrit-Change-Number: 73364 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacks
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72629 ) Change subject: drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacks ...................................................................... drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacks As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/ptn3460/ptn3460.h M src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c 7 files changed, 49 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index d2df04d..7dee222 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -76,13 +76,13 @@ } /* Mainboard provides EDID data. */ - if (mb_get_edid(edid_data) != CB_SUCCESS) { + if (mainboard_ptn3460_get_edid(edid_data) != CB_SUCCESS) { printk(BIOS_ERR, "PTN3460 error: Unable to get EDID data from mainboard.\n"); return; } /* Mainboard decides which EDID table has to be used. */ - edid_tab = mb_select_edid_table(); + edid_tab = mainboard_ptn3460_select_edid_table(); if (edid_tab > PTN_MAX_EDID_NUM) { printk(BIOS_ERR, "PTN3460 error: invalid EDID table (%d) selected.\n", edid_tab); @@ -108,7 +108,7 @@ } /* Mainboard can modify the configuration data. Write back configuration data to PTN3460 if modified by mainboard */ - if (mb_adjust_cfg(&cfg) == CB_SUCCESS) { + if (mainboard_ptn3460_config(&cfg) == CB_SUCCESS) { ptr = (uint8_t *)&cfg; for (i = 0; i < sizeof(struct ptn_3460_config); i++) { val = i2c_dev_writeb_at(dev, PTN_CONFIG_OFF + i, *ptr++); @@ -123,15 +123,15 @@ init_done = true; } -__weak enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +__weak enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { return CB_ERR; } -__weak uint8_t mb_select_edid_table(void) +__weak uint8_t mainboard_ptn3460_select_edid_table(void) { return 0; } -__weak enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg_ptr) +__weak enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg_ptr) { return CB_ERR; } diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index ecd2191..a3fa60b 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -52,8 +52,8 @@ /* We need functions which we can call to get mainboard specific data */ /* These functions can be implemented somewhere else but must exist. */ -extern enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]); -extern uint8_t mb_select_edid_table(void); -extern enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg_ptr); +extern enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]); +extern uint8_t mainboard_ptn3460_select_edid_table(void); +extern enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg_ptr); #endif /* _I2C_PTN3460_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c index 8a20f36..bad4da7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; @@ -31,7 +31,7 @@ * which has to be used. * @return Index of the EDID slot selected for EDID emulation */ -uint8_t mb_select_edid_table(void) +uint8_t mainboard_ptn3460_select_edid_table(void) { return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ } @@ -41,7 +41,7 @@ * @param *cfg_ptr Pointer to the PTN config structure to modify * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error */ -enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg) +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) { const char *hwi_block = "hwinfo.hex"; uint8_t disp_con = 0, color_depth = 0; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c index 39cc274..7f4334e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; @@ -31,7 +31,7 @@ * which has to be used. * @return Index of the EDID slot selected for EDID emulation */ -uint8_t mb_select_edid_table(void) +uint8_t mainboard_ptn3460_select_edid_table(void) { return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ } @@ -41,7 +41,7 @@ * @param *cfg_ptr Pointer to the PTN config structure to modify * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error */ -enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg) +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) { const char *hwi_block = "hwinfo.hex"; uint8_t disp_con = 0, color_depth = 0; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c index c74e90a..320fcc7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -33,7 +33,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; @@ -56,7 +56,7 @@ * which has to be used. * @return Index of the EDID slot selected for EDID emulation */ -uint8_t mb_select_edid_table(void) +uint8_t mainboard_ptn3460_select_edid_table(void) { return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ } @@ -66,7 +66,7 @@ * @param *cfg_ptr Pointer to the PTN config structure to modify * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error */ -enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg) +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) { const char *hwi_block = "hwinfo.hex"; uint8_t disp_con = 0, color_depth = 0; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c index 39cc274..7f4334e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; @@ -31,7 +31,7 @@ * which has to be used. * @return Index of the EDID slot selected for EDID emulation */ -uint8_t mb_select_edid_table(void) +uint8_t mainboard_ptn3460_select_edid_table(void) { return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ } @@ -41,7 +41,7 @@ * @param *cfg_ptr Pointer to the PTN config structure to modify * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error */ -enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg) +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) { const char *hwi_block = "hwinfo.hex"; uint8_t disp_con = 0, color_depth = 0; diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c index 965f62d..a4985c1 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) +enum cb_err mainboard_ptn3460_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; @@ -31,7 +31,7 @@ * which has to be used. * @return Index of the EDID slot selected for EDID emulation */ -uint8_t mb_select_edid_table(void) +uint8_t mainboard_ptn3460_select_edid_table(void) { return 6; /* With this mainboard we use EDID block 6 for emulation in PTN3460. */ } @@ -41,7 +41,7 @@ * @param *cfg_ptr Pointer to the PTN config structure to modify * @return CB_SUCCESS if data was modified and needs to be updated; CB_ERR on error */ -enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg) +enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg) { const char *hwi_block = "hwinfo.hex"; uint8_t disp_con = 0, color_depth = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/72629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Gerrit-Change-Number: 72629 Gerrit-PatchSet: 7 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: merged

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