coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter
by Tim Van Patten (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Chris Wang, Martin Roth, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 ) Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/73124/comment/5873ef2a_b6e24e3f PS6, Line 263: # Remove the sustained_power_limit_mW when STT is enabled : register "sustained_power_limit_mW" = "15000" > It may need to submit another CL if we want to move 'sustained_power_limit_mW' from the baseboard to […] I'm leaning towards Frank's suggestion, since the current comment is not entirely accurate. STT is enabled for Frostflow and Whiterun, but this setting will still be applied (although only via the FSP during boot), so it can't/won't be removed. While `sustained_power_limit_mW` would be duplicated for the boards that need it, we don't want it configured for every board. The current split is: STT Enabled: * Frostflow * Whiterun STT Disabled: * Skyrim * Markarth * Crystaldrift It does look better to set the value in the each `overridetree.cb` that wants it (STT disabled), so it can be removed if/when STT is enabled for that board. Additionally, it prevents `sustained_power_limit_mW` from being set for boards that do have STT enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/73124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Gerrit-Change-Number: 73124 Gerrit-PatchSet: 6 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 16:28:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Keith Hui (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Felix Singer, Angel Pons, Arthur Heymans, Keith Hui, Elyes Haouas. Hello Felix Singer, build bot (Jenkins), Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61540 to look at the new patch set (#7). Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... mb/asus/p8x7x-series: Refactor mainboard_get_spd() This mainboard-specific hook of Sandy/Ivy native RAM init sequence, likely generated by autoport, is the same for all variants. Consolidate them into a separate unit at the baseboard level. Also drop the matching header from variants that do not also support MRC raminit. Build tested on all variants. Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Makefile.inc A src/mainboard/asus/p8x7x-series/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c 8 files changed, 31 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/61540/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix: Update phoenix2 VGA BIOS ID
by Felix Held (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73372 ) Change subject: soc/amd/phoenix: Update phoenix2 VGA BIOS ID ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/73372/comment/fb929e63_a2cbdbac PS1, Line 247: 1002,15c8 > if choose VGA_BIOS_ID=1002,1205 then getting below error: […] it's expected that the first attempt here will fail: rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); then the remapping function map_oprom_vendev gets called and returns the vbios file that we'll need to retrieve. due to the first cbfs_boot_map_optionrom call to expectedly fail, rom_header will be NULL and due to that this code will be run rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16, mapped_vendev & 0xffff); this is how the remapping works. When using 1002,15c8 as VGA_BIOS_ID, things will end up working for the 1002,15c8 id, since map_oprom_vendev will be called unconditionally and due to it remapping the ID, the pci id mismatch check later on will be skipped, but it's not the correct solution. in the case of the 1002,1205 device, having VGA_BIOS_ID set to 1002,15c8 won't work as expected. in that case, cbfs_boot_map_optionrom(dev->vendor, dev->device) would return null and map_oprom_vendev expectedly won't do any remapping, so the cbfs_boot_map_optionrom(mapped_vendev >> 16, mapped_vendev & 0xffff) call will also return null -- To view, visit https://review.coreboot.org/c/coreboot/+/73372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie035baf7a0908e1e6382c1810926647bf7182f6c Gerrit-Change-Number: 73372 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 14:55:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/dell: Add Latitude E6400
by Bill XIE (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Nicholas Chin. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59704 ) Change subject: mb/dell: Add Latitude E6400 ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59704/comment/c63308c4_e8d34540 PS12, Line 32: SD card slot Is this under the traditional PCI bus (1e.0)? If so, the effective content of acpi/ich9_pci_irqs.asl (What the "Method (_PRT)" for "Device (PCIB)" does) had better be collected from the vendor DSDT, as Thinkpad T400 does not have any traditional PCI device. Since this commit has been merged, the improvement of acpi/ich9_pci_irqs.asl should be performed in a new commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/59704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28 Gerrit-Change-Number: 59704 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:49:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTD
by Michał Kopeć (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli, Michał Żygowski, Subrata Banik. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72069 ) Change subject: soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTD ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Gerrit-Change-Number: 72069 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:43:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake/hsphy.c: Handle case with DMA protection
by Michał Kopeć (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli, Michał Żygowski, Subrata Banik, Tim Wawrzynczak, Angel Pons. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68556 ) Change subject: soc/intel/alderlake/hsphy.c: Handle case with DMA protection ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Gerrit-Change-Number: 68556 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:43:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook the VT-d DMA protection option
by Michał Kopeć (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli, Michał Żygowski, Subrata Banik. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68450 ) Change subject: soc/intel/alderlake: Hook the VT-d DMA protection option ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Gerrit-Change-Number: 68450 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:42:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelblocks/vtd: Add VT-d block with DMA protection API
by Michał Kopeć (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Michał Żygowski, Angel Pons. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68449 ) Change subject: intelblocks/vtd: Add VT-d block with DMA protection API ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Gerrit-Change-Number: 68449 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Elias Souza <eliascontato(a)protonmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:40:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mainboard/protectli/vault_ehl: Add initial structure
by Michał Żygowski (Code Review) 03 Mar '23

03 Mar '23

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72407 ) Change subject: mainboard/protectli/vault_ehl: Add initial structure ...................................................................... mainboard/protectli/vault_ehl: Add initial structure This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek(a)3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/protectli/VP2420_back.jpg A Documentation/mainboard/protectli/VP2420_front.jpg A Documentation/mainboard/protectli/VP2420_internal.jpg A Documentation/mainboard/protectli/vp2420.md A configs/config.protectli_vp2420 A src/mainboard/protectli/vault_ehl/Kconfig A src/mainboard/protectli/vault_ehl/Kconfig.name A src/mainboard/protectli/vault_ehl/Makefile.inc A src/mainboard/protectli/vault_ehl/board_info.txt A src/mainboard/protectli/vault_ehl/bootblock.c A src/mainboard/protectli/vault_ehl/data.vbt A src/mainboard/protectli/vault_ehl/devicetree.cb A src/mainboard/protectli/vault_ehl/die.c A src/mainboard/protectli/vault_ehl/dsdt.asl A src/mainboard/protectli/vault_ehl/gpio.h A src/mainboard/protectli/vault_ehl/mainboard.c A src/mainboard/protectli/vault_ehl/romstage.c A src/mainboard/protectli/vault_ehl/vboot-rwa.fmd 19 files changed, 2,218 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 2257059..a1cd9f5 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -168,6 +168,7 @@ - [FW2B / FW4B](protectli/fw2b_fw4b.md) - [FW6A / FW6B / FW6C](protectli/fw6.md) +- [VP2420](protectli/vp2420.md) - [VP4630 / VP4650 / VP4670](protectli/vp46xx.md) ## Roda diff --git a/Documentation/mainboard/protectli/VP2420_back.jpg b/Documentation/mainboard/protectli/VP2420_back.jpg new file mode 100644 index 0000000..eaeb04b --- /dev/null +++ b/Documentation/mainboard/protectli/VP2420_back.jpg Binary files differ diff --git a/Documentation/mainboard/protectli/VP2420_front.jpg b/Documentation/mainboard/protectli/VP2420_front.jpg new file mode 100644 index 0000000..fdac4d1 --- /dev/null +++ b/Documentation/mainboard/protectli/VP2420_front.jpg Binary files differ diff --git a/Documentation/mainboard/protectli/VP2420_internal.jpg b/Documentation/mainboard/protectli/VP2420_internal.jpg new file mode 100644 index 0000000..bc9c2cd --- /dev/null +++ b/Documentation/mainboard/protectli/VP2420_internal.jpg Binary files differ diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md new file mode 100644 index 0000000..68b5da0d --- /dev/null +++ b/Documentation/mainboard/protectli/vp2420.md @@ -0,0 +1,87 @@ +# Protectli Vault VP2420 + +This page describes how to run coreboot on the [Protectli VP2420]. + +![](VP2420_back.jpg) +![](VP2420_front.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. Firmware can be easily +flashed with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip. +This chip is located on the top side of the case (the lid side). One has to +remove 4 top cover screws and lift up the lid. The flash chip is soldered in +under RAM, easily accessed after taking out the memory. Specifically, it's a +KH25L12835F (3.3V) which is a clone of Macronix +MX25L12835F - [datasheet][MX25L12835F]. + +![](VP2420_internal.jpg) + +## Working + +- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux) +- 4 Ethernet ports +- HDMI, DisplayPort +- flashrom +- M.2 WiFi +- M.2 4G LTE +- M.2 SATA and NVMe +- 2.5'' SATA SSD +- eMMC +- Super I/O serial port 0 via front microUSB connector +- SMBus (reading SPD from DIMMs) +- Initialization with Elkhart Lake FSP 2.0 +- SeaBIOS payload (version rel-1.16.0) +- TianoCore UEFIPayload +- Reset switch +- Booting Debian, Ubuntu, FreeBSD + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Celeron J6412 | ++------------------+--------------------------------------------------+ +| PCH | Intel Elkhart Lake | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8613E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Useful links + +- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/) +- [VP2420 Product Page](https://protectli.com/product/vp2420/) +- [Protectli TPM module](https://protectli.com/product/tpm-module/) +- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf) +- [flashrom](https://flashrom.org/Flashrom) diff --git a/configs/config.protectli_vp2420 b/configs/config.protectli_vp2420 new file mode 100644 index 0000000..899a956 --- /dev/null +++ b/configs/config.protectli_vp2420 @@ -0,0 +1,13 @@ +CONFIG_VENDOR_PROTECTLI=y +CONFIG_CBFS_SIZE=0x900000 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_BOARD_PROTECTLI_VP2420=y +CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SD_MMC_TIMEOUT=10 +CONFIG_EDK2_SERIAL_SUPPORT=y diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig new file mode 100644 index 0000000..73e0984 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_PROTECTLI_VP2420 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_ELKHARTLAKE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8613E + select SPI_FLASH_MACRONIX + select INTEL_GMA_HAVE_VBT + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select MEMORY_MAPPED_TPM + +config MAINBOARD_DIR + default "protectli/vault_ehl" + +config MAINBOARD_PART_NUMBER + default "VP2420" + +config MAINBOARD_FAMILY + default "Vault Pro" + +config MAX_CPUS + default 4 + +config CBFS_SIZE + default 0x900000 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VBOOT_SEPARATE_VERSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +endif # BOARD_PROTECTLI_VP2420 diff --git a/src/mainboard/protectli/vault_ehl/Kconfig.name b/src/mainboard/protectli/vault_ehl/Kconfig.name new file mode 100644 index 0000000..2ba1083 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_PROTECTLI_VP2420 + bool "VP2420" diff --git a/src/mainboard/protectli/vault_ehl/Makefile.inc b/src/mainboard/protectli/vault_ehl/Makefile.inc new file mode 100644 index 0000000..9680cbe --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/Makefile.inc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c diff --git a/src/mainboard/protectli/vault_ehl/board_info.txt b/src/mainboard/protectli/vault_ehl/board_info.txt new file mode 100644 index 0000000..04cec3f --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: VP2420 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_ehl/bootblock.c b/src/mainboard/protectli/vault_ehl/bootblock.c new file mode 100644 index 0000000..11bd669 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/bootblock.c @@ -0,0 +1,20 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x29, 0xc1); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/protectli/vault_ehl/data.vbt b/src/mainboard/protectli/vault_ehl/data.vbt new file mode 100644 index 0000000..fe7be17 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/data.vbt Binary files differ diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb new file mode 100644 index 0000000..d21383e --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -0,0 +1,214 @@ +chip soc/intel/elkhartlake + + #register "enable_vtd" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 15, + }" + + register "SaGv" = "SaGv_Enabled" + register "eist_enable" = "1" + + # Enable lpss s0ix + register "s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + #register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32" + #register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0" + #register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0" + + register "tcc_offset" = "5" # TCC of 95C + + # USB 2.0 ports + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Header FUSB1 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WLAN + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Upper + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-C + register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # USB Type-A Lower + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + + # USB 3.x ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Lower + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Muxed + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + # PCIe root ports related UPDs + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" + + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" # Header + register "SataPortsEnable[1]" = "1" # M.2 2280 + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaSdiEnable[0]" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "SkipCpuReplacementCheck" = "1" + + # Enable DDI ports A/B/C + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + register "DdiPortCConfig" = "1" + + # Enable HPD for DDI ports A/B + register "DdiPortAHpd" = "1" + register "DdiPortBHpd" = "1" + + # Enable DDC for DDI ports A/B + register "DdiPortADdc" = "1" + register "DdiPortBDdc" = "1" + + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 08.0 off end # GNA + device pci 09.0 off end # CPU Intel Trace Hub + + device pci 10.0 on end # I2C6 + device pci 10.1 on end # I2C7 + device pci 10.5 on end # Integrated Error Handler + + device pci 11.0 off end # Intel PSE UART0 + device pci 11.1 off end # Intel PSE UART1 + device pci 11.2 off end # Intel PSE UART2 + device pci 11.3 off end # Intel PSE UART3 + device pci 11.4 off end # Intel PSE UART4 + device pci 11.5 off end # Intel PSE UART5 + device pci 11.6 off end # Intel PSE IS20 + device pci 11.7 off end # Intel PSE IS21 + + device pci 12.0 on end # GSPI2 + device pci 12.3 on end # Management Engine UMA Access + device pci 12.4 on end # Management Engine PTT DMA Controller + device pci 12.5 off end # UFS0 + device pci 12.7 off end # UFS1 + + device pci 13.0 off end # Intel PSE GSPI0 + device pci 13.1 off end # Intel PSE GSPI1 + device pci 13.2 off end # Intel PSE GSPI2 + device pci 13.3 off end # Intel PSE GSPI3 + device pci 13.4 off end # Intel PSE GPIO0 + device pci 13.5 off end # Intel PSE GPIO1 + + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI (OTG) + device pci 14.2 on end # Shared RAM + + device pci 15.0 off end # I2C0 + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + + device pci 17.0 on end # SATA + + device pci 18.0 off end # Intel PSE I2C7 + device pci 18.1 off end # Intel PSE CAN0 + device pci 18.2 off end # Intel PSE CAN1 + device pci 18.3 off end # Intel PSE QEP0 + device pci 18.4 off end # Intel PSE QEP1 + device pci 18.5 off end # Intel PSE QEP2 + device pci 18.6 off end # Intel PSE QEP3 + + device pci 19.0 on end # I2C4 + device pci 19.1 off end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 off end # SD + device pci 1a.3 off end # Intel Safety Island + + device pci 1b.0 off end # Intel PSE I2C0 + device pci 1b.1 off end # Intel PSE I2C1 + device pci 1b.2 off end # Intel PSE I2C2 + device pci 1b.3 off end # Intel PSE I2C3 + device pci 1b.4 off end # Intel PSE I2C4 + device pci 1b.5 off end # Intel PSE I2C5 + device pci 1b.6 off end # Intel PSE I2C6 + + device pci 1c.0 on end # RP0 (pcie0 single VC) + device pci 1c.1 on end # RP1 (pcie0 single VC) + device pci 1c.2 on end # RP2 (pcie0 single VC) + device pci 1c.3 off end # RP3 (pcie0 single VC) + device pci 1c.4 on end # RP4 (pcie1 multi VC) + device pci 1c.5 off end # RP5 (pcie2 multi VC) + device pci 1c.6 on end # RP6 (pcie3 multi VC) + + device pci 1d.0 off end # Intel PSE IPC (local host to PSE) + device pci 1d.1 off end # Intel PSE Time-Sensitive Networking GbE 0 + device pci 1d.2 off end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.3 off end # Intel PSE DMA0 + device pci 1d.4 off end # Intel PSE DMA1 + device pci 1d.5 off end # Intel PSE DMA2 + device pci 1d.6 off end # Intel PSE PWM + device pci 1d.7 off end # Intel PSE ADC + + device pci 1e.0 off end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 off end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1e.4 off end # PCH Time-Sensitive Networking GbE + device pci 1e.6 off end # HPET + device pci 1e.7 off end # IOAPIC + + device pci 1f.0 on # eSPI interface + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel cAVS/HDA + device pci 1f.4 on end # SMBUS + device pci 1f.5 on end # PCH SPI (flash & TPM) + device pci 1f.7 off end # PCH Intel Trace Hub + end +end diff --git a/src/mainboard/protectli/vault_ehl/die.c b/src/mainboard/protectli/vault_ehl/die.c new file mode 100644 index 0000000..00366dca --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/die.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <pc80/i8254.h> +#include <delay.h> +#include <gpio.h> + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0; + + gpio_set(GPP_E0, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPP_E0, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_ehl/dsdt.asl b/src/mainboard/protectli/vault_ehl/dsdt.asl new file mode 100644 index 0000000..b60f57b --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/elkhartlake/acpi/southbridge.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/protectli/vault_ehl/gpio.h b/src/mainboard/protectli/vault_ehl/gpio.h new file mode 100644 index 0000000..8aa1224 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/gpio.h @@ -0,0 +1,1611 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* PAD configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - PMC_CORE_VID0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - PMC_CORE_VID1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - ESPI_ALERT2_N */ + /* DW0: 0x44001302, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B2, UP_20K, DEEP, NF4), + + /* GPP_B3 - ESPI_ALERT0_N */ + /* DW0: 0x44001302, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B3, UP_20K, DEEP, NF4), + + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - ESPI_ALERT3_N */ + /* DW0: 0x44001302, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B10, UP_20K, DEEP, NF4), + + PAD_NC(GPP_B11, NONE), + + /* GPP_B12 - PMC_SLP_S0_N */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PMC_PLTRST_N */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + /* DW0: 0x84000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + /* GPIO_RSVD_0 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_0, NONE, DEEP, NF1), + + /* GPIO_RSVD_1 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_1, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T0, NONE), + + /* GPP_T1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T1, NONE), + + /* GPP_T2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T2, NONE), + + /* GPP_T3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T3, NONE), + + /* GPP_T4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T4, NONE), + + /* GPP_T5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T5, NONE), + + /* GPP_T6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T6, NONE), + + /* GPP_T7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T7, NONE), + + /* GPP_T8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T8, NONE), + + /* GPP_T9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T9, NONE), + + /* GPP_T10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T10, NONE), + + /* GPP_T11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T11, NONE), + + /* GPP_T12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T12, NONE), + + /* GPP_T13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T13, NONE), + + /* GPP_T14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T14, NONE), + + /* GPP_T15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G0, NONE), + + /* GPP_G1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G2, NONE), + + /* GPP_G3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G3, NONE), + + /* GPP_G4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G4, NONE), + + /* GPP_G5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G5, NONE), + + /* GPP_G6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G6, NONE), + + /* GPP_G7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G7, NONE), + + /* GPP_G8 - RSVD */ + /* DW0: 0x44000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_G8, NONE), + + /* GPP_G9 - RSVD */ + /* DW0: 0x44000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_G9, NONE), + + /* GPP_G10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G10, NONE), + + /* GPP_G11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G11, NONE), + + /* GPP_G12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G12, NONE), + + /* GPP_G13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G13, NONE), + + /* GPP_G14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G14, NONE), + + /* GPP_G15 - ESPI_IO0 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G15, UP_20K, DEEP, NF1), + + /* GPP_G16 - ESPI_IO1 */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_G16, UP_20K, DEEP, NF1), + + /* GPP_G17 - ESPI_IO2 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G17, UP_20K, DEEP, NF1), + + /* GPP_G18 - ESPI_IO3 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G18, UP_20K, DEEP, NF1), + + /* GPP_G19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPI_APIC_LOCK(GPP_G19, NONE, LEVEL, INVERT, LOCK_CONFIG), + + /* GPP_G20 - ESPI_CS0_N */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G20, UP_20K, DEEP, NF1), + + /* GPP_G21 - ESPI_CLK */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G21, DN_20K, DEEP, NF1), + + /* GPP_G22 - ESPI_RST0_N */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), + + /* GPP_G23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_G23, NONE), + + /* GPIO_RSVD_2 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_2, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_V ------- */ + + /* GPP_V0 - EMMC_CMD */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), + + /* GPP_V1 - EMMC_DATA0 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), + + /* GPP_V2 - EMMC_DATA1 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), + + /* GPP_V3 - EMMC_DATA2 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), + + /* GPP_V4 - EMMC_DATA3 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), + + /* GPP_V5 - EMMC_DATA4 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), + + /* GPP_V6 - EMMC_DATA5 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), + + /* GPP_V7 - EMMC_DATA6 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), + + /* GPP_V8 - EMMC_DATA7 */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), + + /* GPP_V9 - EMMC_RCLK */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), + + /* GPP_V10 - EMMC_CLK */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), + + /* GPP_V11 - EMMC_RST_N */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1), + + /* GPP_V12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_V12, NONE), + + /* GPP_V13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_V13, NONE), + + /* GPP_V14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_V14, NONE), + + /* GPP_V15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_V15, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_H0, NONE), + + /* GPP_H1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H1, NONE), + + /* GPP_H2 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H3, NONE), + + /* GPP_H4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H8, NONE), + + /* GPP_H9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H9, NONE), + + /* GPP_H10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_H10, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_H11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_H11, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_H12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H15, NONE), + + /* GPP_H16 - DDI2_DDC_SCL */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF2), + + /* GPP_H17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H17, NONE), + + /* GPP_H18 - PMC_CPU_C10_GATE_N */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_H18, NONE), + + /* GPP_H19 - DDI2_DDC_SDA */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), + + /* GPP_H20 - DDI2_HPD */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D5, NONE), + + /* GPP_D6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D7, NONE), + + /* GPP_D8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D8, NONE), + + /* GPP_D9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D12, NONE), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D14, NONE), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_D19, NONE), + + /* GPIO_RSVD_3 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_3, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_U ------- */ + + /* GPP_U0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U0, NONE), + + /* GPP_U1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U1, NONE), + + /* GPP_U2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U2, NONE), + + /* GPP_U3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U3, NONE), + + /* GPP_U4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U4, NONE), + + /* GPP_U5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U5, NONE), + + /* GPP_U6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U6, NONE), + + /* GPP_U7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U7, NONE), + + /* GPP_U8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U8, NONE), + + /* GPP_U9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U9, NONE), + + /* GPP_U10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U10, NONE), + + /* GPP_U11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U11, NONE), + + /* GPP_U12 - ISI_CHX_OKNOK_0 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_U12, NONE), + + /* GPP_U13 - ISI_CHX_OKNOK_1 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_U13, NONE), + + /* GPP_U14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U14, NONE), + + /* GPP_U15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U15, NONE), + + /* GPP_U16 - ISI_OKNOK_0 */ + /* DW0: 0x44600702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_U16, NONE), + + /* GPP_U17 - ISI_OKNOK_1 */ + /* DW0: 0x44600702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_U17, NONE), + + /* GPP_U18 - ISI_ALERT_N */ + /* DW0: 0x44600702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_U18, NONE), + + /* GPP_U19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_U19, NONE), + + + /* GPIO_RSVD_4 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_4, NONE, DEEP, NF1), + + /* GPIO_RSVD_5 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_5, NONE, DEEP, NF1), + + /* GPIO_RSVD_6 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_6, NONE, DEEP, NF1), + + /* GPIO_RSVD_7 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_7, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_VGPIO ------- */ + + /* VGPIO_0 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_0, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* VGPIO_5 - GPIO */ + /* DW0: 0x40000003, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_6 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_6, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_7 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_7, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_8 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_8, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_9 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_9, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_10 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_10, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_11 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_11, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_12 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_12, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_13 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_13, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_18 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_18, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_19 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_19, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_20 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_20, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_21 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_21, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_22 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_22, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_23 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_23, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_24 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_24, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_25 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_25, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_30 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_30, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_31 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_31, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_32 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_32, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_33 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_33, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_34 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_34, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_35 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_35, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_36 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_36, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_37 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_37, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO_39 - GPIO */ + /* DW0: 0x44000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(VGPIO_39, 0, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - GPIO */ + /* DW0: 0x04000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPD0, NONE, PWROK, TxLASTRxE, SAME), + + /* GPD1 - PMC_ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - RSVD */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + + /* GPD3 - PMC_PWRBTN_N */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - PMC_SLP_S3_N */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - PMC_SLP_S4_N */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD7 - n/a */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD7, NONE, PWROK, NF1), + + /* GPD8 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD8, 0, PWROK), + + /* GPD9 - RSVD */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + + /* GPD10 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD10, 0, PWROK), + + /* GPD11 - RSVD */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* GPIO_RSVD_8 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPIO_RSVD_8, 0, PWROK), + + /* GPIO_RSVD_9 - n/a */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_9, NONE, PWROK, NF1), + + /* GPIO_RSVD_10 - n/a */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_10, NONE, PWROK, NF1), + + /* GPIO_RSVD_11 - n/a */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_11, NONE, PWROK, NF1), + + /* GPIO_RSVD_12 - n/a */ + /* DW0: 0x00000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_12, NONE, PWROK, NF1), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPIO_RSVD_13 - n/a */ + /* DW0: 0x40000700, DW1: 0x00003c00 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_13, NATIVE, DEEP, NF1), + + /* GPIO_RSVD_14 - n/a */ + /* DW0: 0x40000700, DW1: 0x00003c00 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_14, NATIVE, DEEP, NF1), + + /* GPIO_RSVD_15 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_15, NONE, DEEP, NF1), + + /* GPIO_RSVD_16 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_16, NONE, DEEP, NF1), + + /* GPIO_RSVD_17 - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_CFG_GPIO_HI_Z(GPIO_RSVD_17, NONE, DEEP, TxLASTRxE, SAME), + + /* GPIO_RSVD_18 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_18, NONE, DEEP, NF1), + + /* GPIO_RSVD_19 - n/a */ + /* DW0: 0x40000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_19, NONE, DEEP, NF1), + + /* GPIO_RSVD_20 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_20, NONE, DEEP, NF1), + + /* GPIO_RSVD_21 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_21, NONE, DEEP, NF1), + + /* GPIO_RSVD_22 - n/a */ + /* DW0: 0x40000700, DW1: 0x0003d000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_RSVD_22, DN_20K, DEEP, NF1), + + /* GPIO_RSVD_23 - n/a */ + /* DW0: 0x40000700, DW1: 0x0003d000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_RSVD_23, DN_20K, DEEP, NF1), + + /* GPIO_RSVD_24 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_24, NONE, DEEP, NF1), + + /* GPIO_RSVD_25 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_25, NONE, DEEP, NF1), + + /* GPIO_RSVD_26 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_26, NONE, DEEP, NF1), + + /* GPIO_RSVD_27 - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_CFG_GPIO_HI_Z(GPIO_RSVD_27, NONE, DEEP, TxLASTRxE, SAME), + + /* GPIO_RSVD_28 - n/a */ + /* DW0: 0x40000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_28, NONE, DEEP, NF1), + + /* GPIO_RSVD_29 - n/a */ + /* DW0: 0x40000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_29, NONE, DEEP, NF1), + + /* GPP_S0 - n/a */ + /* DW0: 0x40000700, DW1: 0x00001000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_S0, DN_20K, DEEP, NF1), + + /* GPP_S1 - n/a */ + /* DW0: 0x40000700, DW1: 0x00001000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_S1, DN_20K, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_A0, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_A1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_A1, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_A2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_A2, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_A3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_CFG_GPIO_HI_Z(GPP_A3, NONE, DEEP, TxLASTRxE, SAME), + + /* GPP_A4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A4, NONE), + + /* GPP_A5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A5, NONE), + + /* GPP_A6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A6, NONE), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A9, NONE), + + /* GPP_A10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A10, NONE), + + /* GPP_A11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A12, NONE), + + /* GPP_A13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A14, NONE), + + /* GPP_A15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A17, NONE), + + /* GPP_A18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A18, NONE), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A19, NONE), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A22, NONE), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_VGPIO_USB ------- */ + + /* VGPIO_USB_0 - n/a */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(VGPIO_USB_0, NONE, DEEP, NF1), + + /* VGPIO_USB_1 - n/a */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(VGPIO_USB_1, NONE, DEEP, NF1), + + /* VGPIO_USB_2 - n/a */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(VGPIO_USB_2, NONE, DEEP, NF1), + + /* VGPIO_USB_3 - n/a */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(VGPIO_USB_3, NONE, DEEP, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMB_CLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMB_DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - SMB_ALERT_N */ + /* DW0: 0x44000a02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), + + /* GPP_C3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C3, NONE), + + /* GPP_C4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C4, NONE), + + /* GPP_C5 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_C5, NONE), + + /* GPP_C6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - DNX_FORCE_RELOAD */ + /* DW0: 0x44000b00, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - SML_DATA0 */ + /* DW0: 0x04000f02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - SML_CLK0 */ + /* DW0: 0x04000f02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - SIO_UART2_RXD */ + /* DW0: 0x44001302, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - SIO_UART2_TXD */ + /* DW0: 0x44001300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - SIO_UART2_RTS_N */ + /* DW0: 0x44001300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - SIO_UART2_CTS_N */ + /* DW0: 0x44001302, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F0, NONE), + + /* GPP_F1 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F1, NONE), + + /* GPP_F2 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F2, NONE), + + /* GPP_F3 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F3, NONE), + + /* GPP_F4 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F4, NONE), + + /* GPP_F5 - RSVD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F5, NONE), + + /* GPP_F6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_F7, NONE), + + /* GPP_F8 - ISI_TRACEDATA_0 */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - BOOT_PWR_EN */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_F10, NONE), + + /* GPP_F11 - ISI_TRACECLK */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - ISI_TRACESWO */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - ISI_SWDIO */ + /* DW0: 0x44001702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - ISI_TRACEDATA_1 */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - ISI_TRACEDATA_2 */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - ISI_SWCLK */ + /* DW0: 0x44001702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - ISI_TRACEDATA_3 */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_F23, NONE), + + /* GPIO_RSVD_30 - n/a */ + /* DW0: 0x40000f00, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_30, NONE, DEEP, NF3), + + /* GPIO_RSVD_31 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_31, NONE, DEEP, NF1), + + /* GPIO_RSVD_32 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_32, NONE, DEEP, NF1), + + /* GPIO_RSVD_33 - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_33, NONE, DEEP, NF1), + + /* GPIO_RSVD_34 - n/a */ + /* DW0: 0x40000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_34, NONE, DEEP, NF1), + + /* GPIO_RSVD_35 - n/a */ + /* DW0: 0x40000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPIO_RSVD_35, NONE, DEEP, NF1), + + /* GPIO_RSVD_36 - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_CFG_GPIO_HI_Z(GPIO_RSVD_36, NONE, DEEP, TxLASTRxE, SAME), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - SATA_LED_N */ + /* DW0: 0x84000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), + + /* GPP_E1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - DDI1_HPD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + + /* GPP_E4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - DDI1_DDC_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - DDI1_DDC_SCL */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), + + /* GPP_E8 - SATA_1_DEVSLP */ + /* DW0: 0x04000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E13, NONE), + + /* GPP_E14 - DDI0_HPD */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - RSVD */ + /* DW0: 0x44000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - RSVD */ + /* DW0: 0x44000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - DDI0_DDC_SDA */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF1), + + /* GPP_E19 - DDI0_DDC_SCL */ + /* DW0: 0x44000600, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF1), + + /* GPP_E20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_E22, NONE), + + /* GPP_E23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + /* DW0: 0x44000700, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + /* DW0: 0x44000600, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + /* DW0: 0x44000700, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST_N */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + PAD_NC(GPP_R7, NONE), + +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/protectli/vault_ehl/mainboard.c b/src/mainboard/protectli/vault_ehl/mainboard.c new file mode 100644 index 0000000..388a4e4 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <fsp/api.h> +#include <pc80/i8254.h> +#include <soc/ramstage.h> + +static void mainboard_final(void *chip_info) +{ + beep(1500, 200); +} + + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_ehl/romstage.c b/src/mainboard/protectli/vault_ehl/romstage.c new file mode 100644 index 0000000..7bd1aaf --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/romstage.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <soc/meminit.h> +#include <spd_bin.h> +#include "gpio.h" + +static const struct mb_cfg ddr4_mem_config = { + .UserBd = BOARD_TYPE_MOBILE, + .dq_pins_interleaved = 0, + .vref_ca_config = 2, + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + struct spd_info module_spd_info = { + .read_type = READ_SPD_MEMPTR, + }; + + /* The only DIMM slot is routed to Channel 1 */ + struct spd_block blk = { + .addr_map = { 0x52 }, + }; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + if (blk.spd_array[0] == NULL) + die("No memory detected. Insert DIMM module"); + + module_spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + module_spd_info.spd_spec.spd_data_ptr_info.spd_data_len = (uintptr_t)blk.len; + + /* Set half_populated as false, because DIMM is on Channel 1 */ + memcfg_init(mem_cfg, &ddr4_mem_config, &module_spd_info, false); + + /* Clear Channel 0 DIMM 0 SPD, as the slot is not populated */ + mem_cfg->MemorySpdPtr00 = 0; + /* Return back to coreboot if something goes wrong */ + mem_cfg->ExitOnFailure = 1; + + /* Disable both DIMMs at Channel 0 */ + mem_cfg->DisableDimmChannel0 = 3; + /* Disable DIMM 1 at Channel 1 */ + mem_cfg->DisableDimmChannel1 = 2; + + mem_cfg->Lp4DqsOscEn = 0; +} diff --git a/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd new file mode 100644 index 0000000..3d5a61c --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd @@ -0,0 +1,38 @@ +FLASH 16M { + SI_ALL 7M { + SI_DESC 4K + SI_ME + } + + RW_MISC 424K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_NVRAM(PRESERVE) 24K + } + + CONSOLE 0x20000 + + RW_SECTION_A { + VBLOCK_A 0x2000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + WP_RO@0xC00000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Gerrit-Change-Number: 72407 Gerrit-PatchSet: 17 Gerrit-Owner: Kacper Stojek Gerrit-Reviewer: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/brya/include/ec: Add EC_HOST_EVENT_GPU
by build bot (Jenkins) (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171393): https://review.coreboot.org/c/coreboot/+/73217/comment/c104bd7d_2d7484a2 PS4, Line 19: EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU) |\ trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171393): https://review.coreboot.org/c/coreboot/+/73217/comment/8d7cf6bd_0d41f10e PS4, Line 19: EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU) |\ need consistent spacing around '|' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:25:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2023