coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/brya/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali. Hello Daisuke Nojiri, Caveh Jalali, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73217 to look at the new patch set (#3). Change subject: mb/brya/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... mb/brya/include/ec: Add EC_HOST_EVENT_GPU EC_HOST_EVENT_GPU was renamed from EC_HOST_EVENT_USB_CHARGER and thought to no longer be used. It was subsequently removed in I9e3e0e9b45385766343489ae2d8fc43fb0954923 Add back the mask for this event as it is infact required on certain Brya (Agah) variants. Signed-off-by: Tarun Tuli <taruntuli(a)google.com> BUG=b:216485035,b:258126464,b:266631157 BRANCH=none TEST=D-notifier events are received again from EC Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 --- M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/73217/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/brya/include/ec: Add EC_HOST_EVENT_GPU
by Tarun Tuli (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Daisuke Nojiri, Caveh Jalali. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/brya/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 2 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 03 Mar 2023 13:24:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Update Rex Flash Layout
by Subrata Banik (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, YH Lin, Jamie Ryu, Kapil Porwal, Ivy Jian, Eric Lai, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66288 to look at the new patch set (#15). Change subject: mb/google/rex: Update Rex Flash Layout ...................................................................... mb/google/rex: Update Rex Flash Layout This patch updates the Rex flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. BUG=b:262868089 TEST=Able to enable CSE update on google/rex and have free space to add one more PUNIT FW for support different SoC stepping. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 --- M src/mainboard/google/rex/chromeos.fmd 1 file changed, 40 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/66288/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/66288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Gerrit-Change-Number: 66288 Gerrit-PatchSet: 15 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81
by Kilari Raasi (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Subrata Banik, Ronak Kanabar. Hello build bot (Jenkins), Subrata Banik, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73374 to look at the new patch set (#3). Change subject: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81 ...................................................................... vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81 Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 2 files changed, 1,032 insertions(+), 974 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/73374/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Gerrit-Change-Number: 73374 Gerrit-PatchSet: 3 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by Lean Sheng Tan (Code Review) 03 Mar '23

03 Mar '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/l… Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/include/bootmem.h M src/include/device/device.h M src/include/device/resource.h M src/lib/bootmem.c 5 files changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, but someone else must approve David Hendricks: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 86bf543..e299e54 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -140,6 +140,7 @@ #define LB_MEM_UNUSABLE 5 /* Unusable address space */ #define LB_MEM_VENDOR_RSVD 6 /* Vendor Reserved */ #define LB_MEM_TABLE 16 /* Ram configuration tables are kept in */ +#define LB_MEM_SOFT_RESERVED 0xefffffff /* Specific purpose memory */ }; struct lb_memory { diff --git a/src/include/bootmem.h b/src/include/bootmem.h index 6ccdd88..0478a12 100644 --- a/src/include/bootmem.h +++ b/src/include/bootmem.h @@ -22,6 +22,7 @@ BM_MEM_FIRST = 0x10000, /* First entry in this list */ BM_MEM_RAM, /* Memory anyone can use */ BM_MEM_RESERVED, /* Don't use this memory region */ + BM_MEM_SOFT_RESERVED, /* Specific purpose memory */ BM_MEM_ACPI, /* ACPI Tables */ BM_MEM_NVS, /* ACPI NVS Memory */ BM_MEM_UNUSABLE, /* Unusable address space */ diff --git a/src/include/device/device.h b/src/include/device/device.h index b4b2d20..8a663f0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -428,6 +428,9 @@ fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \ | IORESOURCE_RESERVE) +#define soft_reserved_ram_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_SOFT_RESERVE) + #define bad_ram_resource_kb(dev, idx, basek, sizek) \ reserved_ram_resource_kb((dev), (idx), (basek), (sizek)) diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 9624135..3afdf6a 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -28,6 +28,8 @@ #define IORESOURCE_BRIDGE 0x00080000 /* This is a request to allocate resource about 4G boundary. */ #define IORESOURCE_ABOVE_4G 0x00100000 +/* The resource needs to be soft reserved in the coreboot table */ +#define IORESOURCE_SOFT_RESERVE 0x00200000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_RESERVE 0x10000000 /* The IO resource assignment has been stored in the device */ diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index ea971b6..578ddac 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -50,6 +50,8 @@ return LB_MEM_RESERVED; case BM_MEM_TABLE: return LB_MEM_TABLE; + case BM_MEM_SOFT_RESERVED: + return LB_MEM_SOFT_RESERVED; default: printk(BIOS_ERR, "Unsupported tag %u\n", tag); return LB_MEM_RESERVED; @@ -60,6 +62,7 @@ { const unsigned long cacheable = IORESOURCE_CACHEABLE; const unsigned long reserved = IORESOURCE_RESERVE; + const unsigned long soft_reserved = IORESOURCE_SOFT_RESERVE; struct memranges *bm = &bootmem; initialized = 1; @@ -71,6 +74,7 @@ */ memranges_init(bm, cacheable, cacheable, BM_MEM_RAM); memranges_add_resources(bm, reserved, reserved, BM_MEM_RESERVED); + memranges_add_resources(bm, soft_reserved, soft_reserved, BM_MEM_SOFT_RESERVED); memranges_clone(&bootmem_os, bm); /* Add memory used by CBMEM. */ @@ -136,6 +140,7 @@ { BM_MEM_BL31, "BL31" }, { BM_MEM_OPENSBI, "OPENSBI" }, { BM_MEM_TABLE, "CONFIGURATION TABLES" }, + { BM_MEM_SOFT_RESERVED, "SOFT RESERVED" }, { BM_MEM_RAMSTAGE, "RAMSTAGE" }, { BM_MEM_PAYLOAD, "PAYLOAD" }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 17 Gerrit-Owner: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by Lean Sheng Tan (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Felix Singer, Jonathan Zhang, Julius Werner, Angel Pons, Subrata Banik, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Lance Zhao, Marc Jones, Nico Huber, Philipp Deppenwiese, David Hendricks, Peter Tsung Ho Wu, Ron Minnich. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 16 Gerrit-Owner: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Ron Minnich <rminnich(a)google.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 11:10:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/mtlrvp: Update MTLRVP Flash Layout
by Usha P (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jamie Ryu, Subrata Banik, Kapil Porwal, Balaji Manigandan. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73378 ) Change subject: mb/google/mtlrvp: Update MTLRVP Flash Layout ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/73378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Gerrit-Change-Number: 73378 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 03 Mar 2023 11:07:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Update phoenix2 VGA BIOS ID
by ritul guru (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73372 ) Change subject: soc/amd/phoenix: Update phoenix2 VGA BIOS ID ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/73372/comment/9d6879f7_3d5b4f3c PS1, Line 247: 1002,15c8 > phx2 has VBIOS DID as 15c8, so need to have VGA_BIOS_ID=1002,15c8 in but VBIOS rom has DID 0x1205 wh […] if choose VGA_BIOS_ID=1002,1205 then getting below error: [SPEW ] CBFS DEBUG: _cbfs_alloc(name='pci1002,15c8.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1) [WARN ] CBFS: 'pci1002,15c8.rom' not found. -- To view, visit https://review.coreboot.org/c/coreboot/+/73372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie035baf7a0908e1e6382c1810926647bf7182f6c Gerrit-Change-Number: 73372 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 10:18:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Update phoenix2 VGA BIOS ID
by ritul guru (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73372 ) Change subject: soc/amd/phoenix: Update phoenix2 VGA BIOS ID ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/73372/comment/10ff5212_db1c72d7 PS1, Line 247: 1002,15c8 > shouldn't this be 1002,1205 to match the pci id in the vbios so that both 1205 and 15c8 cases work a […] phx2 has VBIOS DID as 15c8, so need to have VGA_BIOS_ID=1002,15c8 in but VBIOS rom has DID 0x1205 which is handled in map_oprom_vendev(). -- To view, visit https://review.coreboot.org/c/coreboot/+/73372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie035baf7a0908e1e6382c1810926647bf7182f6c Gerrit-Change-Number: 73372 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Mar 2023 10:07:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [TEST] mb/google/brya/skolas: Route I2S2 lines to Discrete BT
by Meera Ravindranath (Code Review) 03 Mar '23

03 Mar '23

Attention is currently required from: Tarun Tuli. Hello Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73416 to look at the new patch set (#2). Change subject: [TEST] mb/google/brya/skolas: Route I2S2 lines to Discrete BT ...................................................................... [TEST] mb/google/brya/skolas: Route I2S2 lines to Discrete BT Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: Ie274edf288531fe6c260275edaa695cf3b3605d3 --- M src/mainboard/google/brya/variants/skolas/fw_config.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/73416/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie274edf288531fe6c260275edaa695cf3b3605d3 Gerrit-Change-Number: 73416 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2023