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Change subject: mb/google/hades: Add baseboard device tree
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add P2SB definition for SPR-SP
......................................................................
Patch Set 1: Code-Review-1
(3 comments)
Patchset:
PS1:
Need a clarification, otherwise looks good to me.
File src/soc/intel/xeon_sp/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/72612/comment/450cfbbb_f6781397
PS1, Line 14: #define P2SBC 0xe0
: #define SBILOCK (1 << 31)
Can you double-check these? The closest thing I can find is "Device Hide(HIDE)" bit 8 in the P2SBC Control register at 0xE0, which exists on both LBG and EBG.
I only found SBILOCK mentioned in the EBG BIOS specification (doc #631063), but that is confusing since it says the bit is P2SB PCI offset E3h[7].
https://review.coreboot.org/c/coreboot/+/72612/comment/93a62ac2_db2818d1
PS1, Line 16: #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)
I guess it's overkill to split headers in this case. I guess we can keep it as-is until we find a need for more p2sb registers?
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73412
to look at the new patch set (#5).
Change subject: mb/google/geralt: Add MAX98390 support for Geralt
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mb/google/geralt: Add MAX98390 support for Geralt
Add a config "USE_MAX98390" to enable MAX98390 support.
MAX98390 is an I2S smart amplifier used in Geralt. It is also the
default speaker for Geralt reference board.
BUG=b:250459803
BRANCH=none
TEST=Verify beep function through CLI in depthcharge successfully.
Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74
Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com>
Signed-off-by: jason-ch chen <Jason-ch.Chen(a)mediatek.com>
---
M src/mainboard/google/geralt/Kconfig
M src/mainboard/google/geralt/chromeos.c
M src/mainboard/google/geralt/gpio.h
M src/mainboard/google/geralt/mainboard.c
M src/soc/mediatek/mt8188/include/soc/addressmap.h
5 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/73412/5
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jason-ch chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73411 )
Change subject: mb/google/geralt: Add mtcmos bus protection for display
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73411/comment/ec82a43f_ad6f3b0c
PS3, Line 9: Add mtcmos for display to enable bus protection while bus hang and
: incomplete bus transactions.
> Enable bus protection for display to avoid bus hang and incomplete bus transaction.
Done
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