coreboot-gerrit November 2023

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[L] Change in coreboot[main]: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
by Felix Singer (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Angel Pons, Martin L Roth, Maximilian Brune, Paul Menzel, Subrata Banik, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66545?usp=email ) Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC ...................................................................... Patch Set 23: (6 comments) File src/mainboard/intel/adlrvp/devicetree_s.cb: https://review.coreboot.org/c/coreboot/+/66545/comment/9d9c0e47_18ccb7f6 : PS22, Line 2: > I created this tree as base for other Alderlake RVP-S boards because there are a few of them and I w […] The settings below apply to all ADL-S boards? File src/mainboard/intel/adlrvp/devicetree_s.cb: https://review.coreboot.org/c/coreboot/+/66545/comment/0b4f1561_e70ea103 : PS23, Line 4: register "usb2_ports[6]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port7 : register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port10 : register "usb2_ports[10]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port11 : r Add the XHCI device in the devicetree and move them into its scope. https://review.coreboot.org/c/coreboot/+/66545/comment/fd047a54_f64218ed : PS23, Line 9: # DDI_PORT_A: Combo PHY A # ADL-S RVP UDIMM 1DPC eDP1.4 Connector : # DDI_PORT_1: Combo PHY B # ADL-S RVP UDIMM 1DPC HDMI 1.4b CRLS : # DDI_PORT_2: Combo PHY C # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # DDI_PORT_3: Combo PHY D # ADL-S RVP UDIMM 1DPC HDMI 2.0b ALS : # DDI_PORT_4: Combo PHY E # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # Enable eDP in PortA #TODO test : #register "ddi_portA_config" = "1" : #[DDI_PORT_A] = DDI_ENABLE_HPD : register "ddi_ports_config" = "{ : [DDI_PORT_1] = DDI_ENABLE_HPD, : [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : [DDI_PORT_3] = DDI_ENABLE_HPD, : [DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : }" Add the iGPU device in the devicetree and move them into its scope. https://review.coreboot.org/c/coreboot/+/66545/comment/3d6c7711_7dd34d1a : PS23, Line 33: [4] = 0, : [5] = 0, Remove, zero by default. https://review.coreboot.org/c/coreboot/+/66545/comment/344f24f2_98a6f272 : PS23, Line 24: register "sata_salp_support" = "1" : register "sata_ports_enable" = "{ : [4] = 1, : [5] = 1, : [6] = 1, : [7] = 1, : }" : : register "sata_ports_dev_slp" = "{ : [4] = 0, : [5] = 0, : [6] = 1, : [7] = 1, : }" Add the SATA device in the devicetree and move them into its scope. File src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb: https://review.coreboot.org/c/coreboot/+/66545/comment/def70c82_87bc5480 : PS23, Line 60: #device ref pcie_rp9 on (doesn't work) : # # PCIE x4 Slot 2 (Document 626352 is wrong here. it states that clk_src should be 16) : # register "pch_pcie_rp[PCH_RP(9)]" = "{ : # .clk_src = 14, : # .clk_req = 14, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end Can be removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/66545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774 Gerrit-Change-Number: 66545 Gerrit-PatchSet: 23 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 14:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX
by Tim Crawford (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Jeremy Soller, Paul Menzel. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78912?usp=email ) Change subject: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78912/comment/550e9c53_5ee6165d : PS1, Line 13: Crucial SODIMMs > Would be nice to add an exact model number. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Gerrit-Change-Number: 78912 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 15 Nov 2023 13:59:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX
by Tim Crawford (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Jeremy Soller, Tim Crawford. Hello Jeremy Soller, Matt DeVillier, Paul Menzel, build bot (Jenkins), ilikenwf, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78912?usp=email to look at the new patch set (#2). Change subject: mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX ...................................................................... mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell(a)gmail.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Tested-by: Levi Portenier <levi(a)system76.com> --- M src/mainboard/system76/rpl/variants/addw3/overridetree.cb M src/mainboard/system76/rpl/variants/bonw15/overridetree.cb M src/mainboard/system76/rpl/variants/serw13/overridetree.cb 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/78912/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Gerrit-Change-Number: 78912 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: acpi/acpigen: drop len assert in acpigen_pop_len
by Felix Held (Code Review) 15 Nov '23

15 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79047?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: acpi/acpigen: drop len assert in acpigen_pop_len ...................................................................... acpi/acpigen: drop len assert in acpigen_pop_len This is already handled as a separate case in the code below, so there's no need for this assert any more. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/acpi/acpigen.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 7479dce..fe36113 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -5,7 +5,6 @@ /* If you need to change this, change acpigen_pop_len too */ #define ACPIGEN_RSVD_PKGLEN_BYTES 3 -#define ACPIGEN_MAXLEN 0xfffff #include <lib.h> #include <string.h> @@ -38,7 +37,6 @@ ASSERT(ltop > 0) char *p = len_stack[--ltop]; len = gencurrent - p; - ASSERT(len <= ACPIGEN_MAXLEN) const size_t payload_len = len - ACPIGEN_RSVD_PKGLEN_BYTES; if (len <= 0x3f + 2) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e Gerrit-Change-Number: 79047 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTES
by Felix Held (Code Review) 15 Nov '23

15 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79046?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTES ...................................................................... acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTES Use a define instead of magic numbers. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/acpi/acpigen.c 1 file changed, 12 insertions(+), 14 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index e5d76ba..7479dce 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -3,12 +3,9 @@ /* How much nesting do we support? */ #define ACPIGEN_LENSTACK_SIZE 10 -/* - * If you need to change this, change acpigen_write_len_f and - * acpigen_pop_len - */ - -#define ACPIGEN_MAXLEN 0xfffff +/* If you need to change this, change acpigen_pop_len too */ +#define ACPIGEN_RSVD_PKGLEN_BYTES 3 +#define ACPIGEN_MAXLEN 0xfffff #include <lib.h> #include <string.h> @@ -29,11 +26,10 @@ { ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1)) len_stack[ltop++] = gencurrent; - /* Reserve 3 bytes for PkgLength. The actual byte values will be written later in the - acpigen_pop_len call. */ - acpigen_emit_byte(0); - acpigen_emit_byte(0); - acpigen_emit_byte(0); + /* Reserve ACPIGEN_RSVD_PKGLEN_BYTES bytes for PkgLength. The actual byte values will + be written later in the corresponding acpigen_pop_len call. */ + for (size_t i = 0; i < ACPIGEN_RSVD_PKGLEN_BYTES; i++) + acpigen_emit_byte(0); } void acpigen_pop_len(void) @@ -43,13 +39,14 @@ char *p = len_stack[--ltop]; len = gencurrent - p; ASSERT(len <= ACPIGEN_MAXLEN) - const size_t payload_len = len - 3; + const size_t payload_len = len - ACPIGEN_RSVD_PKGLEN_BYTES; if (len <= 0x3f + 2) { /* PkgLength of up to 0x3f can be encoded in one PkgLength byte instead of the reserved 3 bytes. Since only 1 PkgLength byte will be written, the payload data needs to be moved by 2 bytes */ - memmove(&p[1], &p[3], payload_len); + memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 2], + &p[ACPIGEN_RSVD_PKGLEN_BYTES], payload_len); /* Adjust the PkgLength to take into account that we only use 1 of the 3 reserved bytes */ len -= 2; @@ -63,7 +60,8 @@ /* PkgLength of up to 0xfff can be encoded in 2 PkgLength bytes instead of the reserved 3 bytes. Since only 2 PkgLength bytes will be written, the payload data needs to be moved by 1 byte */ - memmove(&p[2], &p[3], payload_len); + memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 1], + &p[ACPIGEN_RSVD_PKGLEN_BYTES], payload_len); /* Adjust the PkgLength to take into account that we only use 2 of the 3 reserved bytes */ len -= 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/79046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377 Gerrit-Change-Number: 79046 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: acpi/acpigen: rework acpigen_pop_len for different size PkgLength
by Felix Held (Code Review) 15 Nov '23

15 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79002?usp=email ) Change subject: acpi/acpigen: rework acpigen_pop_len for different size PkgLength ...................................................................... acpi/acpigen: rework acpigen_pop_len for different size PkgLength Previously acpigen_pop_len always wrote a 3 byte PkgLength to the 3 bytes reserved by acpigen_write_len_f. After this patch acpigen_pop_len encodes PkgLength in 1-3 bytes depending on the PkgLength. When less than the 3 bytes that were previously reserved in the corresponding acpigen_write_len_f call are needed for PkgLength, the payload data will be moved back by the number of reserved bytes that aren't needed for the PkgLength. This fixes the problem that the Windows AML parser doesn't like a 3 byte PkgLength being used for the size of the buffer containing UTF-16 strings when the length could be encoded in a single PkgLength byte. In that case, Windows previously ignored the whole SSDT containing this larger than necessary PkgLength encoding. It should however be noted that the ACPI 6.4 spec doesn't specify if it's required to always use the most compact possible encoding of the PkgLength or not. Since iasl generates the shortest possible PkgLength encoding, it's also a good idea to make coreboot's acpigen do the same although it's not required by the specification. With this patch applied, Windows still boots on Mandolin and the time it takes to write the tables doesn't change. To measure the times, the log level in bs_sample_time was increased to BIOS_CRIT and the console log level was increased to BIOS_CRIT too to only get those times as output. BS: BS_WRITE_TABLES run times (exec / console): 8 / 0 ms Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/acpi/acpigen.c 1 file changed, 46 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 57f0d10..e5d76ba 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -38,16 +38,57 @@ void acpigen_pop_len(void) { - int len; + size_t len; ASSERT(ltop > 0) char *p = len_stack[--ltop]; len = gencurrent - p; ASSERT(len <= ACPIGEN_MAXLEN) - /* generate store length for 0xfffff max */ - p[0] = (0x80 | (len & 0xf)); - p[1] = (len >> 4 & 0xff); - p[2] = (len >> 12 & 0xff); + const size_t payload_len = len - 3; + if (len <= 0x3f + 2) { + /* PkgLength of up to 0x3f can be encoded in one PkgLength byte instead of the + reserved 3 bytes. Since only 1 PkgLength byte will be written, the payload + data needs to be moved by 2 bytes */ + memmove(&p[1], &p[3], payload_len); + /* Adjust the PkgLength to take into account that we only use 1 of the 3 + reserved bytes */ + len -= 2; + /* The two most significant bits of PkgLength get the value of 0 to indicate + there are no additional PkgLength bytes. In this case the single PkgLength + byte encodes the length in its lower 6 bits */ + p[0] = len; + /* Adjust pointer for next ACPI bytecode byte */ + acpigen_set_current(p + len); + } else if (len <= 0xfff + 1) { + /* PkgLength of up to 0xfff can be encoded in 2 PkgLength bytes instead of the + reserved 3 bytes. Since only 2 PkgLength bytes will be written, the payload + data needs to be moved by 1 byte */ + memmove(&p[2], &p[3], payload_len); + /* Adjust the PkgLength to take into account that we only use 2 of the 3 + reserved bytes */ + len -= 1; + /* The two most significant bits of PkgLength get the value of 1 to indicate + there's a second PkgLength byte. The lower 4 bits of the first PkgLength + byte and the second PkgLength byte encode the length */ + p[0] = (0x1 << 6 | (len & 0xf)); + p[1] = (len >> 4 & 0xff); + /* Adjust pointer for next ACPI bytecode byte */ + acpigen_set_current(p + len); + } else if (len <= 0xfffff) { + /* PkgLength of up to 0xfffff can be encoded in 3 PkgLength bytes. Since this + is the amount of reserved bytes, no need to move the payload in this case */ + /* The two most significant bits of PkgLength get the value of 2 to indicate + there are two more PkgLength bytes following the first one. The lower 4 bits + of the first PkgLength byte and the two following PkgLength bytes encode the + length */ + p[0] = (0x2 << 6 | (len & 0xf)); + p[1] = (len >> 4 & 0xff); + p[2] = (len >> 12 & 0xff); + /* No need to adjust pointer for next ACPI bytecode byte */ + } else { + /* The case of PkgLength up to 0xfffffff isn't supported at the moment */ + printk(BIOS_ERR, "%s: package length exceeds maximum of 0xfffff.\n", __func__); + } } void acpigen_set_current(char *curr) -- To view, visit https://review.coreboot.org/c/coreboot/+/79002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206 Gerrit-Change-Number: 79002 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/amd/genoa: Add mmio.asl
by Felix Held (Code Review) 15 Nov '23

15 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78895?usp=email ) Change subject: soc/amd/genoa: Add mmio.asl ...................................................................... soc/amd/genoa: Add mmio.asl This patch adds asl code for MMIO device like I2C, UART, GPIO etc. Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>t show Reviewed-on: https://review.coreboot.org/c/coreboot/+/78895 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/amd/genoa/acpi/mmio.asl M src/soc/amd/genoa/acpi/soc.asl 2 files changed, 407 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, but someone else must approve build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/genoa/acpi/mmio.asl b/src/soc/amd/genoa/acpi/mmio.asl new file mode 100644 index 0000000..8ef61a7 --- /dev/null +++ b/src/soc/amd/genoa/acpi/mmio.asl @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/amd/common/acpi/aoac.asl> +#include <soc/aoac_defs.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <amdblocks/acpimmio_map.h> + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + Name (_STA, 0xb) +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Shared, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IGPI + } Else { + IRQN = PGPI + } + If (IRQN == 0x1f || IRQN == 0) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMDI0020") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA0 + } Else { + IRQN = PUA0 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) +} + +Device (FUR1) { + Name (_HID, "AMDI0020") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA1 + } Else { + IRQN = PUA1 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0) +} + +Device (FUR2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA2 + } Else { + IRQN = PUA2 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0) +} + +Device (I2C0) { + Name (_HID, "AMDI0010") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0) +} + +Device (I2C1) { + Name (_HID, "AMDI0010") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0) +} + +Device (I2C2) { + Name (_HID, "AMDI0010") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0) +} + +Device (I2C3) +{ + Name (_HID, "AMDI0010") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +} + +Device (I2C4) +{ + Name (_HID, "AMDI0010") + Name (_UID, 0x4) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II24 + } Else { + IRQN = PI24 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C4, 0) +} + +Device (I2C5) +{ + Name (_HID, "AMDI0010") + Name (_UID, 0x5) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II25 + } Else { + IRQN = PI25 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0) +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "is-rv", 1 }, + }, + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0B) + } +} diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl index 88b0df8..d7684cf 100644 --- a/src/soc/amd/genoa/acpi/soc.asl +++ b/src/soc/amd/genoa/acpi/soc.asl @@ -3,4 +3,6 @@ Scope(\_SB) { /* global utility methods expected within the \_SB scope */ #include "pci_int_defs.asl" + + #include "mmio.asl" } /* End \_SB scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Gerrit-Change-Number: 78895 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/amd/genoa: Add mmio.asl
by Felix Held (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78895?usp=email ) Change subject: soc/amd/genoa: Add mmio.asl ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Gerrit-Change-Number: 78895 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 15 Nov 2023 13:52:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBA...
by Eric Lai (Code Review) 15 Nov '23

15 Nov '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78892?usp=email ) Change subject: mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-A ...................................................................... mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-A Add support for the new memory CXMT CXDB4CBAM-ML-A. BUG=b:304932936 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" And confirm the mainboard boot normally with CXMT CXDB4CBAM-ML-A memory. Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Signed-off-by: Daniel_Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc M src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Daniel Peng: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc index 66919de..8b4d130 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build352956073/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt index 7a6b135..76ab7e0 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build352956073/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +CXDB4CBAM-ML-A 1 (0001) diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt index a6490b2..b93cdbf 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt @@ -1,3 +1,4 @@ H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR K4U6E3S4AB-MGCL +CXDB4CBAM-ML-A -- To view, visit https://review.coreboot.org/c/coreboot/+/78892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Gerrit-Change-Number: 78892 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBA...
by Eric Lai (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Anson Tseng, Daniel Peng, Martin L Roth, Paul Menzel, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78892?usp=email ) Change subject: mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-A ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS2: > you can rebase Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Gerrit-Change-Number: 78892 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 12:34:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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