coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Felix Singer (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Eric Lai, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 12: (1 comment) File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb: https://review.coreboot.org/c/coreboot/+/78594/comment/31a09e47_72296e90 : PS12, Line 43: > nit: space? Oh well. Looks like I messed up a bit here. I used tabs in the other patches. Are you fine with tabs here? -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: acpi: Add PPTT support
by Arthur Heymans (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 18: (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/25668f74_6dabf687 : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > I decided against it, since it is harder to restrict the array size then. We would have to limit the array size based on the number of CPUs times the number of caches per CPU. This would then eat the stack because of recursion. Basically, MAX_CPUS\*MAX_CACHES_PER_CPU\*(16 bytes for the struct)\*MAX_DEPTH_OF_TREE. That should not be the case. In a typical setup all CPUs have the same caches. So this would be the number of different caches in the system. In that case each CPU points to the same cache pointer and you don't need a large array. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 18 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:47:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/skyrim/frostflow: Drop GPIO override for camera shutter
by Karthik Ramasubramanian (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Frank Wu, Jason Nien, Martin Roth, Matt DeVillier. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77678?usp=email ) Change subject: mb/google/skyrim/frostflow: Drop GPIO override for camera shutter ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Gerrit-Change-Number: 77678 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/geralt: Create variant Ciri
by Yidi Lin (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78954?usp=email ) Change subject: mb/google/geralt: Create variant Ciri ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78954/comment/b50cec4c_72224d5c : PS2, Line 12: TEST=emerge-geralt coreboot > Then the TEST= line is unrelated and meaningless in my opinion. This command is correct. `emerge-{board} coreboot` generates coreboot binaries for all variants under `/build/{board}/firmware/{variant}/`. -- To view, visit https://review.coreboot.org/c/coreboot/+/78954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Gerrit-Change-Number: 78954 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/geralt: Create variant Ciri
by Paul Menzel (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Hung-Te Lin, Ruihai Zhou. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78954?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/geralt: Create variant Ciri ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78954/comment/44d1e4d0_a5c734c8 : PS2, Line 9: and enable MAX98390 AMP for it. > I think it should be enough to say this is a variant of geralt Variants can differ. This one does not, so please be more specific. https://review.coreboot.org/c/coreboot/+/78954/comment/6e5d1ad6_43068233 : PS2, Line 12: TEST=emerge-geralt coreboot > No, not all variants. But I think the build bot will do it. Then the TEST= line is unrelated and meaningless in my opinion. -- To view, visit https://review.coreboot.org/c/coreboot/+/78954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Gerrit-Change-Number: 78954 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:16:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Michael Niewöhner (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Eric Lai, Felix Singer. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 12: Code-Review+1 (1 comment) File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb: https://review.coreboot.org/c/coreboot/+/78594/comment/7ebd791c_789bf7ee : PS12, Line 43: nit: space? -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:15:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 18: (6 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/78071/comment/1f4be706_77c691dd : PS17, Line 1204: /* --- header generation --- */ : > Useless comments? Done File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/95835cb5_6a7ed327 : PS17, Line 12: typedef > typedefs are against the style guide. We are still within the ACPI subsystem, where typedefs are common. Would not it be inconsistent to drop them? We dropped the typedefs for the user structs (pptt_topology, ...), since they are used externally, but those typedefs are internal only. https://review.coreboot.org/c/coreboot/+/78071/comment/256a9ab4_5ab6dbfc : PS17, Line 23: = 0x0 > static variables are always initialised at 0. Doesnt hurt to make it explicit, though? https://review.coreboot.org/c/coreboot/+/78071/comment/13ddf98e_314d7524 : PS17, Line 74: u32 *n_caches > Do you need this? you memset cache_refs to 0. […] Thought about this, but then we would have to add an additional element as terminator at the end. Otherwise we would have problems if we search a cache_ref buffer that is full (reading out of bounds). Technically, this is not a problem, but I would like to keep the array as small as possible, since we are in a recursion here. On the other hand, it would be very nice to simplify the signature. If you still think it would be better that way, I can change it :) https://review.coreboot.org/c/coreboot/+/78071/comment/d612e606_6f89e52f : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > Is this not more appropriate to declare this in setup_topology so that all siblings can reuse it? No […] I decided against it, since it is harder to restrict the array size then. We would have to limit the array size based on the number of CPUs times the number of caches per CPU. This would then eat the stack because of recursion. Basically, MAX_CPUS\*MAX_CACHES_PER_CPU\*(16 bytes for the struct)\*MAX_DEPTH_OF_TREE. https://review.coreboot.org/c/coreboot/+/78071/comment/5c865c25_7854e2de : PS17, Line 132: memset(cache_refs, 0x0, sizeof(cache_reference_t) * CONFIG_ACPI_PPTT_MAX_CACHES); : > The ideomatic way in C is "= {}" in the declaration of the variable. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 18 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:14:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 305 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 18 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
by Felix Singer (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Angel Pons, Elyes Haouas, Jason Glenesk, Lennart Eichhorn, Martin L Roth, Patrick Georgi. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70771?usp=email ) Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 ...................................................................... Patch Set 27: (1 comment) Patchset: PS27: Julius, can you help on this issue? https://qa.coreboot.org/job/coreboot-toolchain/1509/testReport/(root)/gcc-c… The romstage exceeds the region size. I have no idea about ARM. So can we just change the region layout or does it have more impact? -- To view, visit https://review.coreboot.org/c/coreboot/+/70771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 27 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:06:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Felix Singer (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Eric Lai, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 12: (1 comment) File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/78594/comment/75606a86_270d291b : PS10, Line 39: (JPCIE6) > No problem with the comment. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 15 Nov 2023 16:02:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023