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Change subject: util/docker: Switch back to root user in jenkins-node
......................................................................
util/docker: Switch back to root user in jenkins-node
Leaving the user as coreboot caused the entrypoint to run as coreboot,
which means we couldn't mount directories or run sshd correctly.
Switching to root at the end of the file fixes this.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948
---
M util/docker/coreboot-jenkins-node/Dockerfile
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/79067/2
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Change subject: util/docker: Switch back to root user in jenkins-node
......................................................................
util/docker: Switch back to root user in jenkins-node
Leaving the user as coreboot caused the entrypoint to run as coreboot,
which means we couldn't mount directories or run sshd correctly.
Switching to root at the end of the file fixes this.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948
---
M util/docker/coreboot-jenkins-node/Dockerfile
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/79067/1
diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile
index 2cd8d78..2c67df5 100644
--- a/util/docker/coreboot-jenkins-node/Dockerfile
+++ b/util/docker/coreboot-jenkins-node/Dockerfile
@@ -89,3 +89,5 @@
echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \
chmod 0700 /home/coreboot/.ssh && \
chmod 0600 /home/coreboot/.ssh/authorized_keys
+USER root
+
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Change subject: mb/google/zork/morphius: Drop touchscreen detection
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78404/comment/67b6915a_2fe3f9ad :
PS3, Line 14: Linux and Windows
> it's pretty much irrelevant. […]
Done
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Change subject: google/*: Clean up Kconfg board selection for Google MTK boards
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/asurada/Kconfig:
https://review.coreboot.org/c/coreboot/+/79063/comment/d6309850_ae0f0d88 :
PS1, Line 11: config BOARD_SPECIFIC_OPTIONS
> So this is something I believe others tried to get rid off too, […]
That's a separate discussion we can have if you want, but personally I think things are ordered better in this version. While Kconfig doesn't care if an option is referenced before it is defined (right?), I think things are easier to read if they logically progress from top to bottom. The effect is not so clear in this file, but if you look at https://review.coreboot.org/c/coreboot/+/79022/1/src/mainboard/google/gru/K… for example, with the version you suggest we'd have a `BOARD_GOOGLE_GRU_COMMON` at the top that has a long list of `select`s, including a bunch that depend on `if GRU_HAS_TPM2`, and then the definition for what `GRU_HAS_TPM2` means would only come below that.
I know some of the Intel boards do things differently, but many of their Kconfig files also have a ton of unnecessary duplication, so I don't think they're necessarily a good model to follow.
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Change subject: mb/google/zork/morphius: Drop touchscreen detection
......................................................................
mb/google/zork/morphius: Drop touchscreen detection
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO
for touchscreen power/enable, and so fail with runtime detection
enabled. Since it only has one touchscreen option, and no SKUs lack a
touchscreen, we can safely assume it is present in all cases.
TEST=build/boot morphius w/4k screen, verify touchscreen enabled in
cbmem and functional in Linux and Windows.
Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/zork/variants/morphius/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/78404/4
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Change subject: google/*: Clean up Kconfg board selection for Google MTK boards
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/asurada/Kconfig:
https://review.coreboot.org/c/coreboot/+/79063/comment/b7d1946d_954ce5c2 :
PS1, Line 11: config BOARD_SPECIFIC_OPTIONS
So this is something I believe others tried to get rid off too,
i.e. what we had on the LHS seems preferred.
(I don't mind it personally)
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Change subject: google/*: Clean up Kconfig board selection for non-MTK Google Arm boards
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/mainboard/google/gru/Kconfig:
https://review.coreboot.org/c/coreboot/+/79022/comment/7b8d7b4e_8bd8ff20 :
PS1, Line 3: # Umbrella option to be selected by variant boards.
This comment seems outdated maybe obsolete (two more below)
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Change subject: acpi: Add PPTT support
......................................................................
Patch Set 18:
(5 comments)
File src/acpi/acpi_pptt.c:
https://review.coreboot.org/c/coreboot/+/78071/comment/06eda3ee_47bcef0f :
PS8, Line 13: * Disclaimer:
: *
: * The generated PPTT table might not be optimized for space, since this
: * implementation creates unique resources (caches) for each CPU provided by
: * the topology tree. Going by the ACPI 6.4 spec, this is fine. We do this to
: * avoid further edge cases and keep the logic as simple as possible.
: *
: * "though less space efficient, it is also acceptable to declare a node
: * for each instance of a resource. In the example above, it would be legal to
: * declare an L1 for each processor."
: *
: * "Compaction of identical resources must be avoided if an implementation requires
: * any resource instance to be referenced uniquely. For example, in the above example,
: * the L1 resource of each processor must be declared using a dedicated structure to
: * permit unique references to it."
: *
> Okay. […]
Marking this as resolved, further details can be discussed separately.
File src/acpi/acpi_pptt.c:
https://review.coreboot.org/c/coreboot/+/78071/comment/12b95de6_68c7f14c :
PS17, Line 12: typedef
> We are still within the ACPI subsystem, where typedefs are common. […]
I was also about to mention the pattern in acpigen code. However,
typedefs there are usually for the structs that represent ACPI tables.
So for this coreboot internal struct, I would also prefer *no* typedef.
No strong feelings though.
https://review.coreboot.org/c/coreboot/+/78071/comment/0295564c_0f8d6902 :
PS17, Line 74: u32 *n_caches
> Forgot to mention, that we also need "n_caches" to index into "cache_refs". […]
I see no need for null-termination as reference_for_cache() already
uses CONFIG_ACPI_PPTT_MAX_CACHES implicitly, by convention. So any
loop over this array could use this globally known upper bound.
Adding a new entry to cache_refs[] would be less convenient, but still
possible: search for the first `.cache != NULL`.
Alternatively, if we just want to simplify the signatures: Pack both
into a single object
```
struct cache_list {
cache_reference_t refs[CONFIG_ACPI_PPTT_MAX_CACHES];
unsigned int n_caches;
};
```
https://review.coreboot.org/c/coreboot/+/78071/comment/bcb483cc_db6e9134 :
PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES];
> > I decided against it, since it is harder to restrict the array size then. […]
They usually have the same kind of cache, but this is about individual
instances of the caches, AIUI. Either the platform code would have to
compact this already (re-use the same `struct pptt_cache` objects) or
we would have to carefully deduplicate cache objects that have the
exact same properties (recursively*), i.e. not compare pointers in
reference_for_cache() but compare in depth (actually what we wanted
to avoid in complexity, remember the disclaimer). To me, the current
logic seems good enough.
*I wouldn't mind a full implementation, it looks like we have most of
the complexity anyway. But we'd have to be careful. Beside comparing
all the data in `struct pptt_cache`, we'd have to follow `.next_level`
too, so something like this wouldn't get deduplicated by accident:
```
L1 (2KiB) L1 (2KiB)
.next_level | .next_level |
v v
L2 (16KiB) L2 (18KiB)
```
(i.e. both L1 look the same, but point to different kinds of L2 caches)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/78071/comment/f35ab5cc_45cd8b2e :
PS3, Line 1442: structures
> > The current structures and code, however, don't express everything ACPI can do […]
Nothing on my end, but this is not my thread ;)
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Change subject: ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
thanks for the uprev. it has been a long time since....
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Change subject: tests/lib: Enforce ux_locales-test with CONFIG_VBOOT
......................................................................
Patch Set 4: Code-Review+2
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