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[S] Change in coreboot[main]: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79085?usp=email ) Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree ...................................................................... nb/amd/pi/00730F01: add CPU and domain ops in devicetree Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 --- M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 2 files changed, 6 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79085/1 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index ef69a9d..1df412e 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01 - device cpu_cluster 0 on end + device cpu_cluster 0 on + ops amd_fam16_mod30_cpu_bus_ops + end device domain 0 on + ops amd_fam16_mod30_pci_domain_ops device pci 0.0 alias gnb on end device pci 0.2 alias iommu off end device pci 1.0 alias gfx off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e8f7abd..3ac94e5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -831,7 +831,7 @@ return NULL; } -static struct device_operations pci_domain_ops = { +struct device_operations amd_fam16_mod30_pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, @@ -863,26 +863,15 @@ } } -static struct device_operations cpu_bus_ops = { +struct device_operations amd_fam16_mod30_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; -static void root_complex_enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") - .enable_dev = root_complex_enable_dev, .final = fam16_finalize, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Gerrit-Change-Number: 79085 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: nb/amd/pi/00730F01: restructure chip ops
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Michał Żygowski, Piotr Król. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79084?usp=email ) Change subject: nb/amd/pi/00730F01: restructure chip ops ...................................................................... nb/amd/pi/00730F01: restructure chip ops Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 6 files changed, 42 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79084/1 diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index d1d394b..6e0c1cd 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 31f5950..75d78eb 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index e036367..b35cdb8 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # LAN1 - device ref gpp_bridge_1 on end # LAN2 - device ref gpp_bridge_2 on end # LAN3 - device ref gpp_bridge_3 on end # LAN4 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 1b9c416..0318d196 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index c977c53..ef69a9d 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,22 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device cpu_cluster 0 on end device domain 0 on - chip northbridge/amd/pi/00730F01 - device pci 0.0 alias gnb on end - device pci 0.2 alias iommu off end - device pci 1.0 alias gfx off end - device pci 1.1 alias gfx_hda off end - device pci 2.0 on end # Dummy Host Bridge, do not disable - device pci 2.1 alias gpp_bridge_0 off end - device pci 2.2 alias gpp_bridge_1 off end - device pci 2.3 alias gpp_bridge_2 off end - device pci 2.4 alias gpp_bridge_3 off end - device pci 2.5 alias gpp_bridge_4 off end - device pci 8.0 alias psp on end - end + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end chip southbridge/amd/pi/hudson device pci 10.0 alias xhci off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bafe5a5..e8f7abd 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -695,12 +695,6 @@ } } -struct chip_operations northbridge_amd_pi_00730F01_ops = { - CHIP_NAME("AMD FAM16 Northbridge") - .enable_dev = 0, - .final = fam16_finalize, -}; - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -886,9 +880,10 @@ } } -struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { +struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") .enable_dev = root_complex_enable_dev, + .final = fam16_finalize, }; /********************************************************************* -- To view, visit https://review.coreboot.org/c/coreboot/+/79084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Gerrit-Change-Number: 79084 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Michał Żygowski, Piotr Król. Hello Michał Żygowski, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79083?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... nb/amd/pi/00730F01: introduce and use chipset devicetree BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/Kconfig A src/northbridge/amd/pi/00730F01/chipset.cb 6 files changed, 116 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79083/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/pcengines/apu2,nb/amd/pi/00730F01: add and use chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79083?usp=email ) Change subject: mb/pcengines/apu2,nb/amd/pi/00730F01: add and use chipset devicetree ...................................................................... mb/pcengines/apu2,nb/amd/pi/00730F01: add and use chipset devicetree BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/Kconfig A src/northbridge/amd/pi/00730F01/chipset.cb 6 files changed, 116 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79083/1 diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 1abcd61..d1d394b 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,32 +1,22 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 off end # USB EHCI0 usb[0:3] not connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -62,18 +52,9 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end # LPC TPM - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 99353f4..8ab538a 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -58,19 +49,10 @@ device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.f on end - end # SIO NCT5104D - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c4975cc..e036367 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # LAN1 - device pci 2.2 on end # LAN2 - device pci 2.3 on end # LAN3 - device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -59,18 +50,9 @@ device pnp 2e.607 off end device pnp 2e.f on end end # SIO NCT5104D - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 0aee11c..1b9c416 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" device pnp 2e.0 off end @@ -58,18 +49,8 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end # LPC TPM - end # LPC 0x439d - - device pci 14.7 off end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 651735a..493bc6a 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -6,6 +6,10 @@ if NORTHBRIDGE_AMD_PI_00730F01 +config CHIPSET_DEVICETREE + string + default "northbridge/amd/pi/00730F01/chipset.cb" + config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb new file mode 100644 index 0000000..c977c53 --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on end + + device domain 0 on + chip northbridge/amd/pi/00730F01 + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end + end + + chip southbridge/amd/pi/hudson + device pci 10.0 alias xhci off end + device pci 11.0 alias sata off end + device pci 12.0 alias ehci_0 off end + device pci 13.0 alias ehci_1 off end + device pci 14.0 alias smbus on end + device pci 14.2 alias hda off end + device pci 14.3 alias lpc_bridge on end + device pci 14.7 alias sdhci off end + device pci 16.0 alias ehci_2 off end + end + + device pci 18.0 alias ht_0 on end + device pci 18.1 alias ht_1 on end + device pci 18.2 alias ht_2 on end + device pci 18.3 alias ht_3 on end + device pci 18.4 alias ht_4 on end + device pci 18.5 alias ht_5 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/arm64: Support calling a trusted monitor
by Benjamin Doron (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: David Milosevic, Julius Werner, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78284?usp=email ) Change subject: arch/arm64: Support calling a trusted monitor ...................................................................... Patch Set 5: (6 comments) File src/arch/arm64/include/armv8/arch/monitor_services.h: PS3: > nit: I'd maybe just call these smc.h / smc. […] As in, the smc instruction, not the SMCCC spec? That's fine, done. https://review.coreboot.org/c/coreboot/+/78284/comment/779b5d46_f9e00098 : PS3, Line 3: #ifndef ARM_ARM64_SMCCC_H > Should match path and filename Done https://review.coreboot.org/c/coreboot/+/78284/comment/b5b21d6b_21f27da9 : PS3, Line 23: SMC_INVALID_PARAMETER = -3, > Where are these from? Are these official in some way or did you make them up? I'm only aware of SMC_ […] These are from the calling convention spec, see https://developer.arm.com/documentation/den0028. As of revision F, return codes are section 7.1. I'll add this as a comment. File src/arch/arm64/monitor_services.c: https://review.coreboot.org/c/coreboot/+/78284/comment/f2c48416_ceadbbe9 : PS3, Line 11: struct smc_args > Returning a big struct by value is ugly (especially if you pass it up through multiple frames). […] Acknowledged https://review.coreboot.org/c/coreboot/+/78284/comment/c6933e26_9618e20a : PS3, Line 18: if (current_el() == EL3) { > In the EL-patch (CB:74798) we now have this decided in Kconfig anyway so you can just write `assert( […] Okay, makes sense to me. The boot path for a platform would be known at compile-time. https://review.coreboot.org/c/coreboot/+/78284/comment/0900761f_97d876e3 : PS3, Line 30: register uint64_t r7 __asm__("x7") = arg6; > This is pretty ugly and I'm not sure it's entirely safe. […] Acknowledged. I'm unfamiliar with Arm assembly, and besides, `assert` is a C macro, so I'll make the actual smc assembly a 'private' function (only smc.c has the prototype). -- To view, visit https://review.coreboot.org/c/coreboot/+/78284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Gerrit-Change-Number: 78284 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 23:14:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Implement initial set of SMBIOS tables
by Benjamin Doron (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: David Milosevic, Julius Werner, Lean Sheng Tan, Martin L Roth, Maximilian Brune. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78285?usp=email ) Change subject: arch/arm64: Implement initial set of SMBIOS tables ...................................................................... Patch Set 5: (6 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/78285/comment/303263ad_dc0ca93a : PS3, Line 919: depends on ARCH_X86 || ARCH_ARM64 > I think adding the 'depends on ARCH_ARM64` is fine, but we should probably add a 'default n if ARCH_ […] That sounds good to me. While it uses TFA services, which happen to need ARM64_CURRENT_EL < 3 (or there's a dead code related compiler error), SMBIOS isn't TFA related so I don't want to tie their configs together. We'll select it in our mainboard. File src/arch/arm64/smbios.c: https://review.coreboot.org/c/coreboot/+/78285/comment/51c7cf98_919f59b4 : PS3, Line 22: processor_id[1] = (midr_el1 >> 32); > The high 32 bits of MIDR_EL1 are reserved 0 anyway. […] That won't return values anything else would return. Is that something to be concerned about? https://review.coreboot.org/c/coreboot/+/78285/comment/b2cedacd_802c476d : PS3, Line 29: char buf[18]; > Uhh... I think this is too short? I think you're cutting off the terminating NUL byte here. […] Oops! Done. https://review.coreboot.org/c/coreboot/+/78285/comment/19d24b69_95c42e15 : PS3, Line 34: implementor > nit: typo […] It's similar to the Linux kernel's output, from memory. https://review.coreboot.org/c/coreboot/+/78285/comment/794b50eb_3f59f4bc : PS3, Line 50: void __weak smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) > Does this need to be implemented per platform? Aren't there architectural ID registers that could be […] There's the MPIDR register, but that only contains the executing CPU's values. So, to get the largest value, we'd need to use MP services to start each possible CPU. Of course, by that point we could also use PSCI_CPU_ON errors to determine which is the largest. The whole thing seemed too roundabout when TFA FDT's usually had CPU nodes we could count instead. The layout of those (as in, nesting) seems common, so the weak implementation could just count that. It's just a matter of getting the pointer to the FDT. https://review.coreboot.org/c/coreboot/+/78285/comment/65baf234_63db196e : PS3, Line 56: #define MAX_CPUS_ENABLED (CONFIG_MAX_CPUS > 0xff ? 0xff : CONFIG_MAX_CPUS) > Note that CONFIG_MAX_CPUS is always 1 on Arm (we don't support SMP in coreboot on Arm and I don't th […] CONFIG_MAX_CPUS is a Kconfig exclusively for SMP's use? Anyways, I'll change this to the macro we actually intend to use here. -- To view, visit https://review.coreboot.org/c/coreboot/+/78285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Gerrit-Change-Number: 78285 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 23:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Implement initial set of SMBIOS tables
by Benjamin Doron (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Benjamin Doron, David Milosevic, Julius Werner, Lean Sheng Tan, Maximilian Brune. Hello David Milosevic, Julius Werner, Lean Sheng Tan, Maximilian Brune, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78285?usp=email to look at the new patch set (#5). Change subject: arch/arm64: Implement initial set of SMBIOS tables ...................................................................... arch/arm64: Implement initial set of SMBIOS tables Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Need to confirm tables are in fact compliant. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/Kconfig A src/arch/arm64/smbios.c M src/arch/arm64/tables.c M src/include/smbios.h 4 files changed, 233 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78285/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Gerrit-Change-Number: 78285 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/arm64: Support calling a trusted monitor
by Benjamin Doron (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Benjamin Doron, David Milosevic, Lean Sheng Tan. Hello David Milosevic, Julius Werner, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78284?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review-1 by Benjamin Doron Change subject: arch/arm64: Support calling a trusted monitor ...................................................................... arch/arm64: Support calling a trusted monitor Implement support for generating an SMC to call a trusted monitor. Some functions are provided to read the SoC ID from the monitor, if supported. Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/arch/arm64/Makefile.inc A src/arch/arm64/include/armv8/arch/smc.h A src/arch/arm64/smc.c A src/arch/arm64/smc_asm.S 4 files changed, 141 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/78284/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I158db0b971aba722b3995d52162146aa406d1644 Gerrit-Change-Number: 78284 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/zork/morphius: Drop touchscreen detection
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78404?usp=email ) Change subject: mb/google/zork/morphius: Drop touchscreen detection ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78404?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Gerrit-Change-Number: 78404 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 23:09:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/docker: Switch back to root user in jenkins-node
by Felix Singer (Code Review) 15 Nov '23

15 Nov '23

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79067?usp=email ) Change subject: util/docker: Switch back to root user in jenkins-node ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948 Gerrit-Change-Number: 79067 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Nov 2023 22:58:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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