coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Yidi Lin (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/6b02e597_898a814d : PS9, Line 16: audio > Can we rename this to be more specific? configure_alc1019 -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 08:35:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variant
by Subrata Banik (Code Review) 16 Nov '23

16 Nov '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79052?usp=email ) Change subject: mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variant ...................................................................... mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variant This patch creates a new variant mtlrvp4es_p_ext_ec. The new variant will support ESx samples. The existing mtlrvp_p_ext_ec variant will support the QS samples. BUG=b:310775573 TEST= Build and boot mtlrvp4es_p_ext_ec. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Kconfig.name 2 files changed, 10 insertions(+), 4 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index f225aa5..26faf91 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -26,6 +26,9 @@ config BOARD_INTEL_MTLRVP_P_EXT_EC select BOARD_EXT_EC_SPECIFIC_OPTIONS + +config BOARD_INTEL_MTLRVP4ES_P_EXT_EC + select BOARD_EXT_EC_SPECIFIC_OPTIONS select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON config BOARD_INTEL_MTLRVP_P_MCHP @@ -61,7 +64,7 @@ config BASEBOARD_DIR string - default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP + default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P || BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP || BOARD_INTEL_MTLRVP4ES_P_EXT_EC config GBB_HWID string @@ -83,7 +86,7 @@ config VARIANT_DIR string default "mtlrvp_p" if BOARD_INTEL_MTLRVP_P - default "mtlrvp_p_ext_ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP + default "mtlrvp_p_ext_ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP || BOARD_INTEL_MTLRVP4ES_P_EXT_EC config DEVICETREE string @@ -99,7 +102,7 @@ choice prompt "ON BOARD EC" default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P - default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP + default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP || BOARD_INTEL_MTLRVP4ES_P_EXT_EC help This option allows you to select the on board EC to use. Select whether the board has Intel EC or/and Chrome EC diff --git a/src/mainboard/intel/mtlrvp/Kconfig.name b/src/mainboard/intel/mtlrvp/Kconfig.name index 9f61aff..696e6e6 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig.name +++ b/src/mainboard/intel/mtlrvp/Kconfig.name @@ -2,7 +2,10 @@ bool "Meteorlake-P RVP" config BOARD_INTEL_MTLRVP_P_EXT_EC - bool "Meteorlake-P RVP with Chrome EC" + bool "Meteorlake-P RVP with Chrome EC for Prod Silicon" + +config BOARD_INTEL_MTLRVP4ES_P_EXT_EC + bool "Meteorlake-P RVP with Chrome EC for non-Prod Silicon" config BOARD_INTEL_MTLRVP_P_MCHP bool "Meteorlake-P RVP with Microchip EC" -- To view, visit https://review.coreboot.org/c/coreboot/+/79052?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c Gerrit-Change-Number: 79052 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[main]: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board
by Arthur Heymans (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Benjamin Doron, Christian Walter, David Milosevic, Lean Sheng Tan, Maximilian Brune, Naresh Solanki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79086?usp=email ) Change subject: mainboard/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... Patch Set 1: Code-Review+1 (6 comments) File Documentation/mainboard/emulation/qemu-sbsa.md: https://review.coreboot.org/c/coreboot/+/79086/comment/db237b30_dbcdee3a : PS1, Line 6: <TF-A> Can building TF-A be added to the makefile? It can be a in a follow-up. https://review.coreboot.org/c/coreboot/+/79086/comment/a7b14c10_bd6afea6 : PS1, Line 6: qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> \ : -pflash ./build/coreboot.rom \ Add a 'qemu' make target so that it is as simple as running 'make qemu'. This can be in a follow-up if you prefer. File src/mainboard/emulation/qemu-sbsa/Kconfig: https://review.coreboot.org/c/coreboot/+/79086/comment/369af4e2_69338b87 : PS1, Line 5: BOARD_SPECIFIC_OPTIONS default to SEPARATE_ROMSTAGE false? Romstage does nothing but initializing cbmem. File src/mainboard/emulation/qemu-sbsa/dsdt.asl: https://review.coreboot.org/c/coreboot/+/79086/comment/cdd43c5f_cbba8eb9 : PS1, Line 419: Device (RES0) : { : Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID : Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings : { : QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, : 0x0000000000000000, // Granularity : SBSA_PCIE_ECAM_BASE, // Range Minimum : SBSA_PCIE_ECAM_LIMIT, // Range Maximum : 0x0000000000000000, // Translation Offset : SBSA_PCIE_ECAM_SIZE, // Length : ,, , AddressRangeMemory, TypeStatic) : }) : Method (_STA) { : Return (0xF) : } : } Drop this. It's in dsdt_top.asl now. File src/mainboard/emulation/qemu-sbsa/flash.fmd: https://review.coreboot.org/c/coreboot/+/79086/comment/ebdafba0_8be09215 : PS1, Line 17: @0x0 CONFIG_ROM_SIZE not needed to specify https://review.coreboot.org/c/coreboot/+/79086/comment/f68e6f3b_98a2d907 : PS1, Line 20: @0x20000 can also be dropped. -- To view, visit https://review.coreboot.org/c/coreboot/+/79086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacc9aaf065e0d153336cbef9a9b5b46a9eb24a53 Gerrit-Change-Number: 79086 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 08:10:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Yu-Ping Wu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Yang Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79064/comment/2dd4c168_fdc49fc0 : PS9, Line 7: /var/chinchou remove File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/52577a15_af212c76 : PS9, Line 16: audio Can we rename this to be more specific? -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 07:40:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Yidi Lin (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/9a4b116e_413a3472 : PS7, Line 43: mt_pll_set_aud_div(48 * KHz); > No, beep sound we can use 26M clock to generate i2s bclk/lrck. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 06:50:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Jiaxin Yu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Jiaxin Yu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/cc05345b_f7fe335e : PS7, Line 43: mt_pll_set_aud_div(48 * KHz); > @jiaxin, does it mean we don't need to configure the clock for ALC5650? No, beep sound we can use 26M clock to generate i2s bclk/lrck. This can simplify the steps of configuring the APLL clock. -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 06:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [Test] Add GD25LQ255E support
by Tyler Wang (Code Review) 16 Nov '23

16 Nov '23

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79087?usp=email ) Change subject: [Test] Add GD25LQ255E support ...................................................................... [Test] Add GD25LQ255E support BUG=none TEST=none Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/drivers/spi/gigadevice.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/79087/1 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index fc2a405..ca0e5fe 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -104,6 +104,13 @@ .fast_read_dual_io_support = 1, }, /* also GD25LB64C */ { + /* GD25LQ255E */ + .id[0] = 0x6019, + .nr_sectors_shift = 13, + .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, + }, + { /* GD25LQ128 */ .id[0] = 0x6018, .nr_sectors_shift = 12, -- To view, visit https://review.coreboot.org/c/coreboot/+/79087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4 Gerrit-Change-Number: 79087 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Ruihai Zhou (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Yang Wu, Yu-Ping Wu. Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 06:25:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Yidi Lin (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Ruihai Zhou, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/fef48ada_40707b6b : PS7, Line 43: mt_pll_set_aud_div(48 * KHz); > Done @jiaxin, does it mean we don't need to configure the clock for ALC5650? -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 06:24:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Yang Wu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Jiaxin Yu, Ruihai Zhou, Yidi Lin, Yu-Ping Wu. Yang Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 9: (3 comments) File src/soc/mediatek/mt8186/include/soc/pll.h: https://review.coreboot.org/c/coreboot/+/79064/comment/d6575505_584851ee : PS7, Line 499: APLL2_CK_HZ = APLL2_HZ, > remove Done https://review.coreboot.org/c/coreboot/+/79064/comment/ed74a837_8524c954 : PS7, Line 531: void mt_pll_set_aud_div(u32 rate); > remove Done File src/soc/mediatek/mt8186/pll.c: https://review.coreboot.org/c/coreboot/+/79064/comment/3d72dc81_69f1cfc2 : PS3, Line 591: void mt_pll_set_aud_div(u32 rate) : { : u32 mclk_div; : u32 apll_clock = APLL2_CK_HZ; : int apll1 = 0; : : if (rate % 11025 == 0) { : /* use APLL1 instead */ : apll1 = 1; : apll_clock = APLL1_CK_HZ; : } : /* I2S1 clock */ : mclk_div = (apll_clock / 256 / rate) - 1; : assert(apll_clock == rate * 256 * (mclk_div + 1)); : : if (apll1) { : /* mclk */ : clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, : 7 << 24); : } else { : /* mclk */ : setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, : 7 << 28); : } : } > We do not use apll clock, remove this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 9 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 06:19:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2023