coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79083?usp=email ) Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79083/comment/2b707106_c0b6ef37 : PS2, Line 16: on end # XHCI HC0 muxed with EHCI 2 : device ref sata on end : device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected : device ref ehci_1 on end # USB EHCI1 usb[4:7] : device ref lpc_bridge on > thoughts on aligning on/off, end, and the comments on tab stops throughout the file? for the mainboard devicetrees this turned out to work rather nicely. i also tried aligning the on/off in the chipset devicetree, but there it didn't improve things -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 11:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: nb/amd/pi/00730F01: restructure chip ops
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król. Hello Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79084?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Matt DeVillier, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: nb/amd/pi/00730F01: restructure chip ops ...................................................................... nb/amd/pi/00730F01: restructure chip ops Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 6 files changed, 42 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79084/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Gerrit-Change-Number: 79084 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król. Hello Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79083?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins) Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... nb/amd/pi/00730F01: introduce and use chipset devicetree BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/Kconfig A src/northbridge/amd/pi/00730F01/chipset.cb 6 files changed, 118 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79083/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6
by Weimin Wu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79091?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6 ...................................................................... mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6 Modify LTE GPIO port of A8&D6. BUG=b:304920262 TEST=LTE function verification is normal Change-Id: I9847029fc7cc5b2c13f2674e4ce26ed9d4f84ae7 Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 24 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79091/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9847029fc7cc5b2c13f2674e4ce26ed9d4f84ae7 Gerrit-Change-Number: 79091 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brya/var/anraggar: Enable CNVi Bluetooth
by Weimin Wu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik, Weimin Wu. Hello Eric Lai, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79055?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/brya/var/anraggar: Enable CNVi Bluetooth ...................................................................... mb/google/brya/var/anraggar: Enable CNVi Bluetooth Enable Bluetooth USB port for CNVi WLAN. BUG=b:304920262 TEST=Bluetooth function verification passed Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79055/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Gerrit-Change-Number: 79055 Gerrit-PatchSet: 3 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6
by Weimin Wu (Code Review) 16 Nov '23

16 Nov '23

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79091?usp=email ) Change subject: mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6 ...................................................................... mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6 Enable Bluetooth USB port for CNVi WLAN. BUG=b:304920262 TEST=LTE function verification is normal Change-Id: I9847029fc7cc5b2c13f2674e4ce26ed9d4f84ae7 Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 29 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79091/1 diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 6eac21a..f74cfbe 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A7 : NC ==> LTE_Present */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), /* A18 : NC ==> HDMI_HPD_SRC*/ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), @@ -47,7 +49,7 @@ /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD ==> EN_PP2800_AVDD*/ - PAD_CFG_GPO(GPP_F18, 0, DEEP), + PAD_CFG_GPO(GPP_F18, 1, DEEP), /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), @@ -80,8 +82,8 @@ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* F16 : NC ==> WWAN_PWR_ENABLE */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* D6 : NC ==> WWAN_PWR_ENABLE */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index bf56363..205db65 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -162,7 +162,7 @@ register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" register "cio2_prt[0]" = "1" device generic 0 on end @@ -199,18 +199,17 @@ end device ref i2c2 on chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" + register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" + register "chip_name" = ""Ov 13b10 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" + register "ssdb.lanes_used" = "4" register "ssdb.vcm_type" = "0x0C" register "vcm_name" = ""VCM0"" register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "link_freq[0]" = "560 * MHz" register "remote_name" = ""IPU0"" register "has_power_resource" = "1" @@ -219,16 +218,15 @@ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "4" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF register "off_seq.ops_cnt" = "4" @@ -240,30 +238,38 @@ device i2c 36 on end end chip drivers/intel/mipi_camera - register "acpi_uid" = "3" + register "acpi_uid" = "2" register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW AF DAC"" + register "chip_name" = ""DW9714 VCM "" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_AVDD + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" - register "chip_name" = ""GT24C08"" + register "chip_name" = ""GT24P64E"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c08"" + register "nvm_compat" = ""atmel,24c64"" device i2c 50 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9847029fc7cc5b2c13f2674e4ce26ed9d4f84ae7 Gerrit-Change-Number: 79091 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer
by Subrata Banik (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79090?usp=email ) Change subject: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Gerrit-Change-Number: 79090 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 10:34:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer
by Dinesh Gehlot (Code Review) 16 Nov '23

16 Nov '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79090?usp=email ) Change subject: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer ...................................................................... MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/79090/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4c63cbf..1da196d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -351,6 +351,7 @@ M: Kapil Porwal <kapilporwal(a)google.com> M: Jakub Czapiga <jacz(a)semihalf.com> M: Eran Mitrani <mitrani(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/mainboard/google/rex/ @@ -887,6 +888,7 @@ M: Kapil Porwal <kapilporwal(a)google.com> M: Jakub Czapiga <jacz(a)semihalf.com> M: Eran Mitrani <mitrani(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/soc/intel/meteorlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/79090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Gerrit-Change-Number: 79090 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer
by Dinesh Gehlot (Code Review) 16 Nov '23

16 Nov '23

Dinesh Gehlot has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79089?usp=email ) Change subject: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer ...................................................................... Abandoned Wrongly pushed to master branch -- To view, visit https://review.coreboot.org/c/coreboot/+/79089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088c27cdb0fd9449940090c482ed6f0556701bbf Gerrit-Change-Number: 79089 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer
by Dinesh Gehlot (Code Review) 16 Nov '23

16 Nov '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79089?usp=email ) Change subject: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer ...................................................................... MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer Change-Id: I088c27cdb0fd9449940090c482ed6f0556701bbf Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/79089/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4c63cbf..1da196d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -351,6 +351,7 @@ M: Kapil Porwal <kapilporwal(a)google.com> M: Jakub Czapiga <jacz(a)semihalf.com> M: Eran Mitrani <mitrani(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/mainboard/google/rex/ @@ -887,6 +888,7 @@ M: Kapil Porwal <kapilporwal(a)google.com> M: Jakub Czapiga <jacz(a)semihalf.com> M: Eran Mitrani <mitrani(a)google.com> +M: Dinesh Gehlot <digehlot(a)google.com> S: Maintained F: src/soc/intel/meteorlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/79089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088c27cdb0fd9449940090c482ed6f0556701bbf Gerrit-Change-Number: 79089 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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