coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: tests: Allow specifying vboot source directory
by Felix Singer (Code Review) 16 Nov '23

16 Nov '23

Felix Singer has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/78849?usp=email ) Change subject: tests: Allow specifying vboot source directory ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/78849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d Gerrit-Change-Number: 78849 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-MessageType: revert

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[XS] Change in coreboot[main]: Revert "tests: Allow specifying vboot source directory"
by Felix Singer (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Jakub Czapiga, Martin L Roth, Yu-Ping Wu. Hello build bot (Jenkins), Martin L Roth, Jakub Czapiga, Yu-Ping Wu, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78852?usp=email to review the following change. Change subject: Revert "tests: Allow specifying vboot source directory" ...................................................................... Revert "tests: Allow specifying vboot source directory" This reverts commit 7713a2f295d9ed9a7023a78e085ce190ee1203fe. Reason for revert: breaks master Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e --- M Makefile M Makefile.inc M tests/Makefile.common 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/78852/1 diff --git a/Makefile b/Makefile index b0a99146..29597c8 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,6 @@ additional-dirs := -VBOOT_SOURCE ?= $(abspath 3rdparty/vboot) VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) COREBOOT_EXPORTS := COREBOOT_EXPORTS diff --git a/Makefile.inc b/Makefile.inc index 2f810d5..e382518 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -460,6 +460,7 @@ endif CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj) +VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h CPPFLAGS_common += -include $(src)/include/rules.h diff --git a/tests/Makefile.common b/tests/Makefile.common index 9cc79d7..e51d253 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -36,7 +36,7 @@ TEST_INCLUDES += -I$(src) -I$(src)/include -I$(src)/commonlib/include \ -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \ - -I$(VBOOT_SOURCE)/firmware/include + -I$(top)/3rdparty/vboot/firmware/include # Path for Kconfig autoheader TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) -- To view, visit https://review.coreboot.org/c/coreboot/+/78852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e Gerrit-Change-Number: 78852 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer
by Paul Menzel (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79090?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: MAINTAINERS: Add myself as METEORLAKE SOC and GOOGLE REX MB maintainer ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79090/comment/8cb16069_91f45080 : PS1, Line 7: myself It’s not useful, when reading the shortlog. ;-) I suggest: > MAINTAINERS: Add Dinesh Gehlot for METEORLAKE SOC and GOOGLE REX MB -- To view, visit https://review.coreboot.org/c/coreboot/+/79090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Gerrit-Change-Number: 79090 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 13:43:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Create variant Ciri
by Paul Menzel (Code Review) 16 Nov '23

16 Nov '23

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78954?usp=email ) Change subject: mb/google/geralt: Create variant Ciri ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78954/comment/6f4a1246_cd073939 : PS2, Line 9: and enable MAX98390 AMP for it. Last comment: > I mean, this commit isn't even creating anything - it's just > adding the name to the existing Kconfig files. I agree, but you only know, once you looked at the diff. This is what I tried to improve. Anyway, thank you for taking the time to comment. I also agree, it is not such a big issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/78954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Gerrit-Change-Number: 78954 Gerrit-PatchSet: 5 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 16 Nov 2023 13:40:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Michael Niewöhner (Code Review) 16 Nov '23

16 Nov '23

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... mb/supermicro/x11: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 5 files changed, 54 insertions(+), 92 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index d98c20e..254486c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -28,56 +28,12 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 off end # CPU PCIe Port 10 (x16) - device pci 01.1 off end # CPU PCIe Port 11 (x8) - device pci 01.2 off end # CPU PCIe Port 12 (x4) - device pci 02.0 off end # Integrated Graphics Device (IGD) - device pci 04.0 on end # SA thermal subsystem - device pci 05.0 off end # Imaging Unit - device pci 08.0 off end # Gaussion Mixture Model (GMM) - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 off end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1b.0 off end # PCH PCIe Port 17 - device pci 1b.1 off end # PCH PCIe Port 18 - device pci 1b.2 off end # PCH PCIe Port 19 - device pci 1b.3 off end # PCH PCIe Port 20 - device pci 1c.0 off end # PCH PCIe Port 1 - device pci 1c.1 off end # PCH PCIe Port 2 - device pci 1c.2 off end # PCH PCIe Port 3 - device pci 1c.3 off end # PCH PCIe Port 4 - device pci 1c.4 off end # PCH PCIe Port 5 - device pci 1c.5 off end # PCH PCIe Port 6 - device pci 1c.6 off end # PCH PCIe Port 7 - device pci 1c.7 off end # PCH PCIe Port 8 - device pci 1d.0 off end # PCH PCIe Port 9 - device pci 1d.1 off end # PCH PCIe Port 10 - device pci 1d.2 off end # PCH PCIe Port 11 - device pci 1d.3 off end # PCH PCIe Port 12 - device pci 1d.4 off end # PCH PCIe Port 13 - device pci 1d.5 off end # PCH PCIe Port 14 - device pci 1d.6 off end # PCH PCIe Port 15 - device pci 1d.7 off end # PCH PCIe Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # SPI #0 - device pci 1e.6 off end # SDXC - device pci 1f.0 on # LPC Interface + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref heci1 on end + device ref sata on end + device ref lpc_espi on chip superio/common device pnp 2e.0 on end end @@ -85,12 +41,7 @@ device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI Controller - device pci 1f.6 off end # GbE - device pci 1f.7 off end # Intel Trace Hub + device ref smbus on end + device ref fast_spi on end end end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 4d54afe..98bfb04 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -41,44 +41,47 @@ }" device domain 0 on - device pci 01.0 on + device ref peg0 on + # Slot JPCIE3 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" - end # CPU PCIE Slot (JPCIE3) - device pci 01.1 on # CPU PCIE Slot (JPCIE2) + end + device ref peg1 on + # Slot JPCIE2 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" end - device pci 02.0 on end # Integrated Graphics Device (No Output) - device pci 1c.0 on # PCI Express Port 1 + device ref igpu on end + device ref pcie_rp1 on register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end - device pci 1c.1 on # PCI Express Port 2 + device ref pcie_rp2 on register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end - device pci 1c.2 on # PCI Express Port 3 only on -LN4F + device ref pcie_rp3 on register "PcieRpEnable[2]" = "1" device pci 00.0 on end # GbE end - device pci 1c.3 on # PCI Express Port 4 only on -LN4F + device ref pcie_rp4 on register "PcieRpEnable[3]" = "1" device pci 00.0 on end # GbE end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end - device pci 1c.6 on # PCI Express Port 7 + device ref pcie_rp7 on register "PcieRpEnable[6]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + device ref pcie_rp9 on + # Slot JPCIE1 register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 56b8f9c..b46b220 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -40,30 +40,32 @@ }" device domain 0 on - device pci 01.0 on end # unused - device pci 01.1 on # PCIE Slot (JPCIE1) + device ref peg0 on end # unused + device ref peg1 on + # Slot JPCIE1 register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end - device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + device ref pcie_rp1 on + # Slot JPCIE1 register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end - device pci 1c.2 on # PCI Express Port 3 + device ref pcie_rp3 on device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi use pch_gpio as gpio_dev register "post_complete_gpio" = "GPP_B20" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 66206a6..29252fe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -36,25 +36,29 @@ device domain 0 on subsystemid 0x15d9 0x0896 inherit - device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + device ref peg0 on + # Slot JPCIE6 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" end - device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + device ref peg1 on + # Slot JPCIE7 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" end - device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + device ref pcie_rp1 on + # Slot JPCIE4 register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + device ref pcie_rp5 on + # Slot JPCIE5 register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1d.0 on # PCH PCIe Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" @@ -62,7 +66,7 @@ subsystemid 0x15d9 0x1533 end end - device pci 1d.1 on # PCH PCIe Port 10 + device ref pcie_rp10 on register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" @@ -70,7 +74,7 @@ subsystemid 0x15d9 0x1533 end end - device pci 1d.2 on # PCH PCIe Port 11 + device ref pcie_rp11 on register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieRpAdvancedErrorReporting[10]" = "1" @@ -78,7 +82,7 @@ device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi use pch_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" # JPB1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index c5c2778..29babda 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -42,32 +42,34 @@ }" device domain 0 on - device pci 01.0 on + device ref peg0 on + # Slot JSXB1B smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" - end # CPU PCIE Slot JSXB1B - device pci 1c.0 on # PCI Express Port 1 + end + device ref pcie_rp1 on register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end - device pci 1c.1 on # PCI Express Port 2 + device ref pcie_rp2 on register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end - device pci 1d.0 on # PCI Express Port 9 (Slot JSXB2) + device ref pcie_rp9 on + # Slot JSXB2 register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1d.4 on # PCI Express Port 13 + device ref pcie_rp13 on register "PcieRpEnable[12]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 16 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Michael Niewöhner (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Eric Lai, Felix Singer. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 13:17:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Felix Singer (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Eric Lai, Michael Niewöhner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 15: (1 comment) File src/mainboard/supermicro/x11-lga1151-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/78594/comment/9389bf31_32ee399a : PS14, Line 35: > you missed one, sorry 😄 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 16 Nov 2023 13:05:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Felix Singer (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Eric Lai, Felix Singer, Michael Niewöhner. Hello Eric Lai, Michael Niewöhner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78594?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Michael Niewöhner, Verified+1 by build bot (Jenkins) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... mb/supermicro/x11: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 5 files changed, 54 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78594/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
by Nico Huber (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79085?usp=email ) Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Gerrit-Change-Number: 79085 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Nov 2023 12:59:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Nico Huber (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79083?usp=email ) Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79083/comment/13d8b9c7_8bd23caf : PS2, Line 16: on end # XHCI HC0 muxed with EHCI 2 : device ref sata on end : device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected : device ref ehci_1 on end # USB EHCI1 usb[4:7] : device ref lpc_bridge on > for the mainboard devicetrees this turned out to work rather nicely. […] I think it would make the few devices that are `on` by default stick out. RN I had to look closer. -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 12:56:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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