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Change subject: [RFC] drivers/option: Add forms in cbtables
......................................................................
Patch Set 20:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74121/comment/9ab7a766_f382326a :
PS18, Line 20: cursed forms representation
> Config Option Data - COD? […]
How about we keep the acronym, but using different words?
Configure Firmware at Runtime - CFR
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Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
Patch Set 5: Code-Review+1
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Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
......................................................................
Patch Set 4: Code-Review+1
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Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
Patch Set 5:
(1 comment)
File src/northbridge/amd/pi/00730F01/chipset.cb:
https://review.coreboot.org/c/coreboot/+/79083/comment/6f73a71f_3c5405ff :
PS4, Line 8: on
> two spaces after 'on' makes these all line up nicely
Done
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I'd like you to reexamine a change. Please visit
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Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
......................................................................
nb/amd/pi/00730F01: add CPU and domain ops in devicetree
Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
---
M src/northbridge/amd/pi/00730F01/chipset.cb
M src/northbridge/amd/pi/00730F01/northbridge.c
2 files changed, 6 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79085/4
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Change subject: nb/amd/pi/00730F01: restructure chip ops
......................................................................
nb/amd/pi/00730F01: restructure chip ops
Since this chip is a SoC and also to bring the chipset devicetree more
in line with the chipset devicetree of Sandy Bridge, merge the chip
operations of the northbridge's root complex and the northbridge itself
into one chip operations structure and use it at the top level of the
devicetree.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2
---
M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
M src/northbridge/amd/pi/00730F01/chipset.cb
M src/northbridge/amd/pi/00730F01/northbridge.c
6 files changed, 42 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79084/4
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The following approvals got outdated and were removed:
Code-Review+1 by Matt DeVillier
Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
nb/amd/pi/00730F01: introduce and use chipset devicetree
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI
devices. The HDA controller in the FCH at function 2 of device 0x14 on
bus 0 was missing in the mainboard's devicetrees.
TEST=PC Engines APU2 still boots and doesn't show any new problems
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Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979
---
M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
M src/northbridge/amd/pi/00730F01/Kconfig
A src/northbridge/amd/pi/00730F01/chipset.cb
6 files changed, 118 insertions(+), 148 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79083/5
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Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79083/comment/2650fdbf_92c82114 :
PS2, Line 16: on end # XHCI HC0 muxed with EHCI 2
: device ref sata on end
: device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected
: device ref ehci_1 on end # USB EHCI1 usb[4:7]
: device ref lpc_bridge on
> Yes, I'd prefer alignment. I'm not overzealous about it, though, and wouldn't […]
Oh, missed PS4 and your later comment...
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Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79083/comment/c7a3f6e8_84b85e1b :
PS2, Line 16: on end # XHCI HC0 muxed with EHCI 2
: device ref sata on end
: device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected
: device ref ehci_1 on end # USB EHCI1 usb[4:7]
: device ref lpc_bridge on
> i'm not sure if i understood correctly what you meant; did you mean that tab-aligning the on/off in […]
Yes, I'd prefer alignment. I'm not overzealous about it, though, and wouldn't
be when formatting the code. For instance, the comment on the host bridge
seems to be the only thing that's way too long. But that line looks different
than the others anyway, so I would make an exception there.
Making things look more tabular, makes it easier to see exceptions, e.g.
the on/off here:
```
chip southbridge/amd/pi/hudson
device pci 10.0 alias xhci off end
device pci 11.0 alias sata off end
device pci 12.0 alias ehci_0 off end
device pci 13.0 alias ehci_1 off end
device pci 14.0 alias smbus on end
device pci 14.2 alias hda off end
device pci 14.3 alias lpc_bridge on end
device pci 14.7 alias sdhci off end
device pci 16.0 alias ehci_2 off end
end
```
(um, looks like Gerrit uses 4-char tabs here?)
I probably wouldn't mind exceptions to the 96-char rule. I think that's
a good compromise for C code that looks more ragged anyway. Tables are
different.
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Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/northbridge/amd/pi/00730F01/chipset.cb:
https://review.coreboot.org/c/coreboot/+/79083/comment/8bf4c255_2208fab1 :
PS4, Line 8: on
two spaces after 'on' makes these all line up nicely
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