coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: nb/amd/pi/00730F01: restructure chip ops
by Matt DeVillier (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Michał Żygowski, Piotr Król. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79084?usp=email ) Change subject: nb/amd/pi/00730F01: restructure chip ops ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Gerrit-Change-Number: 79084 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 03:40:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Matt DeVillier (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Michał Żygowski, Piotr Król. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79083?usp=email ) Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79083/comment/6089a400_94d4edac : PS2, Line 16: on end # XHCI HC0 muxed with EHCI 2 : device ref sata on end : device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected : device ref ehci_1 on end # USB EHCI1 usb[4:7] : device ref lpc_bridge on thoughts on aligning on/off, end, and the comments on tab stops throughout the file? -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 03:38:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/supermicro/x11: Make use of chipset devicetree
by Eric Lai (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Felix Singer, Michael Niewöhner. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email ) Change subject: mb/supermicro/x11: Make use of chipset devicetree ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Gerrit-Change-Number: 78594 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 16 Nov 2023 02:44:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/osiris: Update power limit values for RPL CPU
by Nick Vaccaro (Code Review) 16 Nov '23

16 Nov '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79059?usp=email ) Change subject: mb/google/brya/var/osiris: Update power limit values for RPL CPU ...................................................................... mb/google/brya/var/osiris: Update power limit values for RPL CPU Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/osiris/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 5ba725b..7ff5925 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -63,6 +63,12 @@ }, }" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + device domain 0 on device ref igpu on chip drivers/gfx/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/79059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Gerrit-Change-Number: 79059 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya/var/osiris: Update power limit values for RPL CPU
by Nick Vaccaro (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: David Wu, Nick Vaccaro, Paul Menzel, Ren Kuo, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79059?usp=email ) Change subject: mb/google/brya/var/osiris: Update power limit values for RPL CPU ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Gerrit-Change-Number: 79059 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Nov 2023 02:34:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 19: (2 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/42d69a21_ca96631c : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; Our current platform code makes sure to point to the same `struct pptt_cache` object whenever two caches share the same `next_level`. For instance, for the qemu-sbsa board we have this ``` /* * L2 cache (LLC) */ struct pptt_cache l2 = { .next_level = NULL }; /* * L1I cache */ struct pptt_cache l1i = { .next_level = &l2 }; /* * L1D cache */ struct pptt_cache l1d = { .next_level = &l2 }; /* * private resources of a cpu core. Same for * each core. */ struct pptt_cpu_resources core_resources = { .cache = &l1i, .next = &(struct pptt_cpu_resources) { .cache = &l1d, .next = NULL } }; ``` I think we can leave it for the platform code. I dont see a relevant advantage from deduplicating caches within the ACPI generation code. Maybe we could add a small note for the user, that the PPTT code is sensitive to the pointers you pass in. > Is this not more appropriate to declare this in setup_topology so that all siblings can reuse it? Now you create these references for each call of new_pptt_cpu. return reference_for_cache in pptt_cache if !0? I have moved the cache list to `setup_topology`, so this is done. Keeping the discussion open though, in case someone wants reply. Otherwise feel free to mark as done. File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78071/comment/a43fdcbc_52a3816c : PS3, Line 1442: structures > Nothing on my end, but this is not my thread ;) Okay, then I think we can close this. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 19 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 16 Nov 2023 02:29:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 19: (3 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/c4ea6f7a_c24e0d43 : PS17, Line 12: typedef > I was also about to mention the pattern in acpigen code. However, […] Removing typedefs would elongate the signatures even more, so I would like to keep them, if possible. Also, right now, one can easily distinguish between structures that are passed in by user (struct without typedefs) and structures solely used by the ACPI subsystem (structs with typedefs). https://review.coreboot.org/c/coreboot/+/78071/comment/8de644c5_974db633 : PS17, Line 23: = 0x0 > Doesnt hurt to make it explicit, though? Done https://review.coreboot.org/c/coreboot/+/78071/comment/8c312332_4ecc4547 : PS17, Line 74: u32 *n_caches > I see no need for null-termination as reference_for_cache() already […] I dont like the idea of iterating over the array only to insert a new element. I will try to pack it all in a struct, although not my favorite approach either. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 19 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 16 Nov 2023 02:04:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 324 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 19 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for A...
by Jiaxin Yu (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Yang Wu, Yidi Lin, Yu-Ping Wu. Jiaxin Yu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79064?usp=email ) Change subject: mb/google/corsola/var/chinchou: Configure I2C and I2S interface for ALC5650 ...................................................................... Patch Set 7: (4 comments) File src/mainboard/google/corsola/mainboard.c: https://review.coreboot.org/c/coreboot/+/79064/comment/0b548061_d5def007 : PS7, Line 43: mt_pll_set_aud_div(48 * KHz); We don't use apll clock, so we can remove this. File src/soc/mediatek/mt8186/include/soc/pll.h: https://review.coreboot.org/c/coreboot/+/79064/comment/05e0a98f_2e1d9e93 : PS7, Line 499: APLL2_CK_HZ = APLL2_HZ, remove https://review.coreboot.org/c/coreboot/+/79064/comment/b8208931_5208defb : PS7, Line 531: void mt_pll_set_aud_div(u32 rate); remove File src/soc/mediatek/mt8186/pll.c: https://review.coreboot.org/c/coreboot/+/79064/comment/1fc3b6ec_98ad76fc : PS3, Line 591: void mt_pll_set_aud_div(u32 rate) : { : u32 mclk_div; : u32 apll_clock = APLL2_CK_HZ; : int apll1 = 0; : : if (rate % 11025 == 0) { : /* use APLL1 instead */ : apll1 = 1; : apll_clock = APLL1_CK_HZ; : } : /* I2S1 clock */ : mclk_div = (apll_clock / 256 / rate) - 1; : assert(apll_clock == rate * 256 * (mclk_div + 1)); : : if (apll1) { : /* mclk */ : clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, : 7 << 24); : } else { : /* mclk */ : setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); : clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, : mclk_div << 8); : /* bclk */ : clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, : 7 << 28); : } : } > Leave this part for Jiaxin to review. We do not use apll clock, remove this. -- To view, visit https://review.coreboot.org/c/coreboot/+/79064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Gerrit-Change-Number: 79064 Gerrit-PatchSet: 7 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jiaxin Yu <jiaxin.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 01:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/osiris: Update power limit values for RPL CPU
by Peter Ou (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: David Wu, Nick Vaccaro, Paul Menzel, Ren Kuo, Subrata Banik. Peter Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79059?usp=email ) Change subject: mb/google/brya/var/osiris: Update power limit values for RPL CPU ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > @Peter, would you please provide thermal report? Thanks. Yes, upload the compare setting before and after in the issue tracker number. https://partnerissuetracker.corp.google.com/issues/310834985 -- To view, visit https://review.coreboot.org/c/coreboot/+/79059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Gerrit-Change-Number: 79059 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Nov 2023 01:06:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2023