coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: sb/intel/bd82x6x/lpc: Enable more clock gatings
by Patrick Rudolph (Code Review) 18 Nov '23

18 Nov '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79146?usp=email ) Change subject: sb/intel/bd82x6x/lpc: Enable more clock gatings ...................................................................... sb/intel/bd82x6x/lpc: Enable more clock gatings Follow BWG and enable dynamic clock gating for all devices. - Enable SMBUS clock gating - Enable SATA clock gating TEST: Lenovo X220 still boots over SATA. Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79146/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0cf7b9c..eb8d35d 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -361,8 +361,10 @@ reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); + /* DMI clock gating */ pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + /* PCIe clock gating */ pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); pch_iobp_update(0xEC004000, ~0U, (1 << 7)); @@ -378,12 +380,17 @@ reg32 &= ~(1 << 20); reg32 |= (1 << 19); reg32 |= (1 << 0); + reg32 |= (1 << 5); reg32 |= (0xf << 1); RCBA32(CG) = reg32; RCBA32_OR(0x38c0, 0x7); RCBA32_OR(0x36d4, 0x6680c004); RCBA32_OR(0x3564, 0x3); + + /* SATA clock gating */ + pch_iobp_update(0xEA007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEA004000, ~0U, (1 << 7)); } static void pch_set_acpi_mode(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/79146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Gerrit-Change-Number: 79146 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL
by Patrick Rudolph (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78609?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL ...................................................................... cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs MSR_PKGC_IRTL with values from BWG. Test: Lenovo X220 still boots. Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78609/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16 Gerrit-Change-Number: 78609 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG
by Patrick Rudolph (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78608?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG ...................................................................... cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG Now that those registers are only written once set the lock bit to protect it from runtime changes. TEST: Lenovo X220 still boots. Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/78608/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c Gerrit-Change-Number: 78608 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Write MSRs in scope package only once
by Patrick Rudolph (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Felix Held, Patrick Rudolph, Paul Menzel. Hello Angel Pons, Felix Held, Keith Hui, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78607?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: cpu/intel/model_206ax: Write MSRs in scope package only once ...................................................................... cpu/intel/model_206ax: Write MSRs in scope package only once Write MSRs that are in scope package only once by checking for the BSP bit. While this improves performance a bit it also has the benefit that registers can be safely locked down without the need for semaphores. TEST: Lenovo X220 still boots. Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 66 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/78607/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031 Gerrit-Change-Number: 78607 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brya/var/anraggar: Enable LTE module
by Weimin Wu (Code Review) 18 Nov '23

18 Nov '23

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79166?usp=email ) Change subject: mb/google/brya/var/anraggar: Enable LTE module ...................................................................... mb/google/brya/var/anraggar: Enable LTE module Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/79166/1 diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 925a622..117e5f1 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -32,6 +32,8 @@ /* GPP_C6 : NC ==> TCHSCR_REPORT_EN */ PAD_CFG_GPO(GPP_C6, 1, DEEP), + /* D6 : NC ==> WWAN_PWR_ENABLE */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ @@ -56,7 +58,6 @@ /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), - /* H12 : UART0_RTS# ==> SD_PERST_L ==> NC*/ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : UART0_CTS# ==> EN_PP3300_SD_X ==> NC */ @@ -85,8 +86,6 @@ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* D6 : NC ==> WWAN_PWR_ENABLE */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/79166?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Gerrit-Change-Number: 79166 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/geralt: Remove unnecessary delay for MIPI panel
by Yu-Ping Wu (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79109?usp=email ) Change subject: mb/google/geralt: Remove unnecessary delay for MIPI panel ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Gerrit-Change-Number: 79109 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-CC: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 07:16:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Lean Sheng Tan (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Milosevic, Julius Werner, Martin L Roth, Maximilian Brune, Nico Huber. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74798/comment/8d13c027_5a9801da : PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards. > I agree with Julius, this is not the way forward. […] first, in my opinion , it’s very demeaning and over simplified to just called this “coreboot as a payload”, even this “payload” took us months to work to enable it. I think many people might don’t understand the gravity of this effort while taking it for granted for what x86 coreboot had to overcome to make it in the state today - yes, there are many technically smart people sacrificing their own freeetime working on the x86 coreboot code; never overlook the fact that there were also many engineers and some management with good faith work tirelessly either in Intel or Google or in companies using Intel chips pushing coreboot adoption and OSF ideology from within, some even has to take on personal price to make things happen. and FSP 1 is far from perfect from what we have today - it was the journey itself that slowly make us a much workable and more acceptable stage of Open source firmware we have on x86. so for arm ecosystem today, we don’t have this luxury anymore - much lesser coreboot or open source fighters have the leverage to push for the good ideas within the company, many earlier fighters have left. the whole industry are moving really fast, even while risc-v ecosystem is heavily invested in edk2 now. So, if we shut ourselves off to even make it possible to enable major Arm SoC platforms today, and don’t even have the patience to start the journey to build the coreboot ecosystem for arm and make it better, then you have to accept the fact that there will be edk2 and close source firmware everywhere, in arm or disc-v, in the next 5 years. in that time, we will have no leverage at all, even on x86 (currently we can still put on significant pressure and made intel changed its original plan to push for FSP at reset), especially when everyone has moved on to ARM and risc-V, so Intel will have no choice but to move to FSP at reset again because “it is industry standard now as arm and risc-v is doing it”. and don’t complain about it anymore when it’s edk2 and close source firmware, because we turned our back behind them at the first place, hence no way to slowly influence the industry to move to better standard/ flow. -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 9 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 06:43:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/anraggar: Fix Type-C & DP functions
by Weimin Wu (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79165?usp=email ) Change subject: mb/google/brya/var/anraggar: Fix Type-C & DP functions ...................................................................... mb/google/brya/var/anraggar: Fix Type-C & DP functions Due to TCPC0 & TCPC1 exchanged compare to Neried design. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/79165/1 diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 6ba43c3..cfb77da 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -364,8 +364,8 @@ end device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] + use conn0 as mux_conn[1] + use conn1 as mux_conn[0] device pnp 0c09.0 on end end end @@ -373,12 +373,12 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port + use usb2_port2 as usb2_port use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port2 as usb2_port + use usb2_port1 as usb2_port use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Gerrit-Change-Number: 79165 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya/var/anraggar: Enable ILITEK touchscreen
by Weimin Wu (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79164?usp=email ) Change subject: mb/google/brya/var/anraggar: Enable ILITEK touchscreen ...................................................................... mb/google/brya/var/anraggar: Enable ILITEK touchscreen Fix GPP_C6 configration for ILITEK touchscreen. BUG=b:304920262 TEST=touchscreen function works Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79164/1 diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 686ae8b..925a622 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -29,6 +29,9 @@ /* B11 : NC ==> EN_PP3300_WLAN_X*/ PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* GPP_C6 : NC ==> TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 1, DEEP), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 9c6492d..6ba43c3 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -223,8 +223,6 @@ register "generic.reset_delay_ms" = "200" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "12" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)" - register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 41 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Gerrit-Change-Number: 79164 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/brya/var/anraggar: Add MIPI camera device
by Weimin Wu (Code Review) 18 Nov '23

18 Nov '23

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79163?usp=email ) Change subject: mb/google/brya/var/anraggar: Add MIPI camera device ...................................................................... mb/google/brya/var/anraggar: Add MIPI camera device Enable MIPI camera for anraggar project. BUG=b:309518095 TEST=Camera APP working Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: wuweimin <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 26 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/79163/1 diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index cdbb72f..686ae8b 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -32,7 +32,7 @@ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */ PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), /* D13 : NC ==> EN_PP1800_WCAM_X */ - PAD_CFG_GPO_LOCK(GPP_D13, 0, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG), /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL ==> NC */ PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), @@ -49,7 +49,7 @@ /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD ==> EN_PP2800_AVDD*/ - PAD_CFG_GPO(GPP_F18, 0, DEEP), + PAD_CFG_GPO(GPP_F18, 1, DEEP), /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index defb8e6..9c6492d 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -207,7 +207,7 @@ register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" register "cio2_prt[0]" = "1" device generic 0 on end @@ -244,18 +244,17 @@ end device ref i2c2 on chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" + register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" + register "chip_name" = ""Ov 13b10 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" + register "ssdb.lanes_used" = "4" register "ssdb.vcm_type" = "0x0C" register "vcm_name" = ""VCM0"" register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "link_freq[0]" = "560 * MHz" register "remote_name" = ""IPU0"" register "has_power_resource" = "1" @@ -264,16 +263,15 @@ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "4" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF register "off_seq.ops_cnt" = "4" @@ -285,30 +283,38 @@ device i2c 36 on end end chip drivers/intel/mipi_camera - register "acpi_uid" = "3" + register "acpi_uid" = "2" register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW AF DAC"" + register "chip_name" = ""DW9714 VCM "" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_AVDD + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" - register "chip_name" = ""GT24C08"" + register "chip_name" = ""GT24P64E"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c08"" + register "nvm_compat" = ""atmel,24c64"" device i2c 50 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Gerrit-Change-Number: 79163 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2023