coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: sb/intelbd82x6x/sata: Enable SATA clock gating
by Patrick Rudolph (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79146?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review-1 by Patrick Rudolph, Verified-1 by build bot (Jenkins) Change subject: sb/intelbd82x6x/sata: Enable SATA clock gating ...................................................................... sb/intelbd82x6x/sata: Enable SATA clock gating Program SATA IOBP and enable clock gating after port enable bits have been written. TEST: Lenovo X220 still boots over SATA. Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/sata.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79146/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Gerrit-Change-Number: 79146 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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[NoOp] Change in coreboot[main]: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
by Matt DeVillier (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Christian Walter, Lean Sheng Tan, Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79020?usp=email ) Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79020/comment/363fa120_5ba8cb95 : PS2, Line 9: but update it : based on ADL-P MR5 FSP > what is BDB? it's essentially the VBT version, as reported by intelvbtool or DisCon. If the VBT BDB doesn't match that what FSP is expecting, then FSP GOP display init will fail. -- To view, visit https://review.coreboot.org/c/coreboot/+/79020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Gerrit-Change-Number: 79020 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 19:35:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge: Fix unitialized variable issue
by Keith Hui (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Jérémy Compostella, Keith Hui, Martin L Roth, Martin Roth, Paul Menzel. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79093?usp=email ) Change subject: nb/intel/sandybridge: Fix unitialized variable issue ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Sorry, my bad, was tired. 😞 Please merge before 4.22 tape out. -- To view, visit https://review.coreboot.org/c/coreboot/+/79093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Gerrit-Change-Number: 79093 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 18:17:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/x86: Support SMBASE relocation-only use-case
by Benjamin Doron (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Martin L Roth, Matt DeVillier, Matt DeVillier, Maulik Vaghela, Raul Rangel, Subrata Banik, Tarun, Tarun Tuli, ron minnich. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70376?usp=email ) Change subject: cpu/x86: Support SMBASE relocation-only use-case ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > that explains why smmstore won't work for that. […] As discussed in the leadership meeting, we don't want to pull UEFI code in for verification, and locking the store is an idea brought up on https://review.coreboot.org/c/coreboot/+/79095, which I've addressed there. Currently, UefiPayload has code that's generic for Intel platforms, so long as it's passed the register offsets. That code is in cbtable.c. Support for AMD platforms could be added to UefiPayload, then, for the current design, we would pass the required registers. I'm already aware that one driver there needs enhancement... Intel platforms can trigger an SMI for entering S3/S4/S5, but they don't have to. In coreboot, I believe, it's almost just a print-and-return deal. Board dependent SMI handlers aren't supported. That does make the case for sharing SMM, I'm working on that. -- To view, visit https://review.coreboot.org/c/coreboot/+/70376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec96bab19cdcf80622756f02a3dae49b42036c8d Gerrit-Change-Number: 70376 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 18 Nov 2023 18:05:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Documentation: Describe how SMMSTORE can be used safely
by Benjamin Doron (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Patrick Georgi. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79095?usp=email ) Change subject: Documentation: Describe how SMMSTORE can be used safely ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Looks pretty good to me. From "the boot process ... […] I've thought more about a possible LOCK command, and I don't think it works for secure boot unfortunately. UEFI variable stores are always append-only. When overwriting, it invalidates the old one and writes a new one. So just switching to append-only isn't an option. We also can't select a range to protect, that would probably contain other variables, some are very prone to move. It would have to be a list of ranges (UEFI code would probably have to search by hand *and* consider fault-tolerance. I'm not looking forward to that). But still: when to lock? DxeReadyToLock is an idea, before untrusted code can run. Or one of the end-of-firmware events. But the problem is, the user and OS only gets to customise secure boot *after* ready-to-lock. UEFI's model allows this: a physically present user is authorised in the setup menu, and the OS can update if the update is signed by existing keys. -- To view, visit https://review.coreboot.org/c/coreboot/+/79095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48f44d3416d210e1e6b19d18cad787e380ffeebc Gerrit-Change-Number: 79095 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Sat, 18 Nov 2023 17:56:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel: Support NO_SMM on modern SoCs
by Benjamin Doron (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Kapil Porwal, Maulik Vaghela, Patrick Rudolph, Paul Menzel, Sean Rhodes, Subrata Banik, Tarun Tuli, Werner Zeh. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70377?usp=email ) Change subject: soc/intel: Support NO_SMM on modern SoCs ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/common/block/cpu/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/70377/comment/3fe2fa47_9e53729d : PS14, Line 217: *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); > The codepath for this one is weird. It's a constant for a CPU. I don't understand this point? Because it's silicon specific, the pointer isn't passed to the platform driver to be filled. For the specific driver I've written in the follow-up, returning "SKIP_SMM_INIT" means that `perm_smbase` and `perm_smsize` were set to the invalid state "0" which will disable SMM inside mp_init. But I don't want to rely on that here. This pointer still needs to be determined. Then it returns without doing work, as requested. -- To view, visit https://review.coreboot.org/c/coreboot/+/70377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94b66020a249714bc4f430de1d1f7808b26261cf Gerrit-Change-Number: 70377 Gerrit-PatchSet: 14 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 17:30:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79171?usp=email ) Change subject: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree Since the EHCI controllers in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the EHCI device operations to the PCI devices during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/usb_ehci.c 2 files changed, 3 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/79171/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 39d63c6..7ef6b95 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -25,7 +25,7 @@ device pci 16.2 alias me_ide_r off end # Management Engine IDE-R device pci 16.3 alias me_kt off end # Management Engine KT device pci 19.0 alias gbe off end # Intel Gigabit Ethernet - device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 + device pci 1a.0 alias ehci2 off ops bd82x6x_usb_ehci_ops end device pci 1b.0 alias hda off ops bd82x6x_azalia_ops end # High Definition Audio device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 @@ -35,7 +35,7 @@ device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end # PCIe Port #6 device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 - device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 + device pci 1d.0 alias ehci1 off ops bd82x6x_usb_ehci_ops end device pci 1e.0 alias pci_bridge off ops bd82x6x_pci_bridge_ops end device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 1cb260a..f05d932 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -90,7 +90,7 @@ .set_subsystem = &usb_ehci_set_subsystem, }; -static struct device_operations usb_ehci_ops = { +struct device_operations bd82x6x_usb_ehci_ops = { .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -98,12 +98,3 @@ .ops_pci = &lops_pci, .acpi_name = usb_ehci_acpi_name, }; - -static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, - 0 }; - -static const struct pci_driver pch_usb_ehci __pci_driver = { - .ops = &usb_ehci_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Gerrit-Change-Number: 79171 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79170?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree Since the XHCI controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the XHCI device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/usb_xhci.c 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/79170/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 29e9d7f..39d63c6 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -19,7 +19,7 @@ device pci 06.0 alias peg60 off ops sandybridge_nb_pcie_rp_ops end # PEG60 chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH - device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) + device pci 14.0 alias xhci off ops bd82x6x_usb_xhci_ops end # XHCI Controller only on 7 series device pci 16.0 alias mei1 on end # Management Engine Interface 1 device pci 16.1 alias mei2 off end # Management Engine Interface 2 device pci 16.2 alias me_ide_r off end # Management Engine IDE-R diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 5607b16..f71a505 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -41,7 +41,7 @@ return "XHC"; } -static struct device_operations usb_xhci_ops = { +struct device_operations bd82x6x_usb_xhci_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -49,11 +49,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = xhci_acpi_name, }; - -static const unsigned short pci_device_ids[] = { 0x1e31, 0 }; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Gerrit-Change-Number: 79170 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79169?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree Since the PCI bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the PCI bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/pci.c 2 files changed, 2 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/79169/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index f11fd2f..29e9d7f 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -36,7 +36,7 @@ device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 - device pci 1e.0 alias pci_bridge off end # PCI bridge + device pci 1e.0 alias pci_bridge off ops bd82x6x_pci_bridge_ops end device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 device pci 1f.3 alias smbus on ops bd82x6x_smbus_ops end diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 382506b..2294421 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -35,7 +35,7 @@ pci_write_config16(dev, SECSTS, reg16); } -static struct device_operations device_ops = { +struct device_operations bd82x6x_pci_bridge_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -43,15 +43,3 @@ .scan_bus = pci_scan_bridge, .ops_pci = &pci_dev_ops_pci, }; - -static const unsigned short pci_device_ids[] = { - 0x2448, /* Mobile */ - 0x244e, /* Desktop */ - 0 -}; - -static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Gerrit-Change-Number: 79169 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79168?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree Since the SMBus controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the SMBus device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/smbus.c 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79168/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index c7fbceb3..f11fd2f 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -39,7 +39,7 @@ device pci 1e.0 alias pci_bridge off end # PCI bridge device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 - device pci 1f.3 alias smbus on end # SMBus + device pci 1f.3 alias smbus on ops bd82x6x_smbus_ops end device pci 1f.5 alias sata2 off end # SATA Controller 2 device pci 1f.6 alias thermal off end # Thermal end diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 0cb6d00..d2ca247 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -28,7 +28,7 @@ return "SBUS"; } -static struct device_operations smbus_ops = { +struct device_operations bd82x6x_smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -38,11 +38,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = smbus_acpi_name, }; - -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 }; - -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Gerrit-Change-Number: 79168 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2023