coreboot-gerrit November 2023

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79167?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/lpc.c 2 files changed, 2 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/79167/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 00ec492..c7fbceb3 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -37,7 +37,7 @@ device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge - device pci 1f.0 alias lpc on end # LPC bridge + device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 device pci 1f.3 alias smbus on end # SMBus device pci 1f.5 alias sata2 off end # SATA Controller 2 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0cf7b9c..5d1a7bf 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -658,7 +658,7 @@ memcpy(spi_config, &config->spi, sizeof(*spi_config)); } -static struct device_operations device_ops = { +struct device_operations bd82x6x_lpc_bridge_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -671,26 +671,3 @@ .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, }; - -/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and - * Intel C200 Series Chipset - */ - -static const unsigned short pci_device_ids[] = { - 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, - 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, - 0x1c52, 0x1c53, 0x1c54, 0x1c55, 0x1c56, 0x1c57, 0x1c58, 0x1c59, 0x1c5a, - 0x1c5b, 0x1c5c, 0x1c5d, 0x1c5e, 0x1c5f, - - 0x1e41, 0x1e42, 0x1e43, 0x1e44, 0x1e45, 0x1e46, 0x1e47, 0x1e48, 0x1e49, - 0x1e4a, 0x1e4b, 0x1e4c, 0x1e4d, 0x1e4e, 0x1e4f, 0x1e50, 0x1e51, 0x1e52, - 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, - 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f, - - 0 }; - -static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Gerrit-Change-Number: 79167 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
by Sergii Dmytruk (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Arthur Heymans, Krystian Hebel, Sergii Dmytruk. Hello Krystian Hebel, Martin L Roth, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67065?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER ...................................................................... 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER Signing is performed with test keys by default, set CONFIG_SIGNING_KEYS_DIR to non-empty value to use other keys. Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M .gitmodules A 3rdparty/open-power-signing-utils M Makefile.inc M src/soc/ibm/power9/Kconfig M src/soc/ibm/power9/Makefile.inc 5 files changed, 55 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/67065/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/67065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Gerrit-Change-Number: 67065 Gerrit-PatchSet: 22 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79118?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/azalia.c 2 files changed, 2 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index c3c35c1..a08b1bd 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -26,7 +26,7 @@ device pci 16.3 alias me_kt off end # Management Engine KT device pci 19.0 alias gbe off end # Intel Gigabit Ethernet device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 - device pci 1b.0 alias hda off end # High Definition Audio + device pci 1b.0 alias hda off ops bd82x6x_azalia_ops end # High Definition Audio device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end # PCIe Port #3 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 97884c6..ddaa8a1 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -122,7 +122,7 @@ return "HDEF"; } -static struct device_operations azalia_ops = { +struct device_operations bd82x6x_azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -130,11 +130,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = azalia_acpi_name, }; - -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; - -static const struct pci_driver pch_azalia __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Gerrit-Change-Number: 79118 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79117?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are visible and working. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/pcie.c 2 files changed, 9 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 38a53d5..c3c35c1 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -27,14 +27,14 @@ device pci 19.0 alias gbe off end # Intel Gigabit Ethernet device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 device pci 1b.0 alias hda off end # High Definition Audio - device pci 1c.0 alias pcie_rp1 off end # PCIe Port #1 - device pci 1c.1 alias pcie_rp2 off end # PCIe Port #2 - device pci 1c.2 alias pcie_rp3 off end # PCIe Port #3 - device pci 1c.3 alias pcie_rp4 off end # PCIe Port #4 - device pci 1c.4 alias pcie_rp5 off end # PCIe Port #5 - device pci 1c.5 alias pcie_rp6 off end # PCIe Port #6 - device pci 1c.6 alias pcie_rp7 off end # PCIe Port #7 - device pci 1c.7 alias pcie_rp8 off end # PCIe Port #8 + device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 + device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 + device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end # PCIe Port #3 + device pci 1c.3 alias pcie_rp4 off ops bd82x6x_pcie_rp_ops end # PCIe Port #4 + device pci 1c.4 alias pcie_rp5 off ops bd82x6x_pcie_rp_ops end # PCIe Port #5 + device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end # PCIe Port #6 + device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 + device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge device pci 1f.0 alias lpc on end # LPC bridge diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 325bfd2..13f16f8 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -258,7 +258,7 @@ pch_pcie_pm_late(dev); } -static struct device_operations device_ops = { +struct device_operations bd82x6x_pcie_rp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -268,15 +268,3 @@ .acpi_name = pch_pcie_acpi_name, .ops_pci = &pci_dev_ops_pci, }; - -static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Gerrit-Change-Number: 79117 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[NoOp] Change in coreboot[main]: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
by Lean Sheng Tan (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Christian Walter, Matt DeVillier, Paul Menzel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79020?usp=email ) Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79020/comment/2a4b4a7f_3840535b : PS2, Line 9: but update it : based on ADL-P MR5 FSP > can you specify the BDB version used? makes it easier to track down breakages in the future what is BDB? -- To view, visit https://review.coreboot.org/c/coreboot/+/79020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Gerrit-Change-Number: 79020 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 18 Nov 2023 16:22:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: Use SA devid to identify PC type
by Lean Sheng Tan (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Keith Hui, Matt DeVillier, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78826?usp=email ) Change subject: nb/intel/sandybridge: Use SA devid to identify PC type ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Gerrit-Change-Number: 78826 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 18 Nov 2023 16:18:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cross-repo-cherrypick: Update downstream branch
by Matt DeVillier (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Felix Held, Jon Murphy, Martin L Roth, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79143?usp=email ) Change subject: cross-repo-cherrypick: Update downstream branch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f67ef4fb175a4e4896b5bed81d5ae1cdddb827 Gerrit-Change-Number: 79143 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 18 Nov 2023 15:57:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign gma ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79114?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/sandybridge: assign gma ops in chipset devicetree ...................................................................... nb/intel/sandybridge: assign gma ops in chipset devicetree Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and graphics works in UEFI Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/gma.c 2 files changed, 2 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 9fb1701..38a53d5 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -14,7 +14,7 @@ device pci 01.0 alias peg10 off end # PEG10 device pci 01.1 alias peg11 off end # PEG11 device pci 01.2 alias peg12 off end # PEG12 - device pci 02.0 alias igd off end # vga controller + device pci 02.0 alias igd off ops sandybridge_gma_func0_ops end # vga controller device pci 04.0 alias dev4 off end # Device 4 device pci 06.0 alias peg60 off end # PEG60 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 3eed5cc..2304a04 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -640,7 +640,7 @@ dev->enabled = 0; } -static struct device_operations gma_func0_ops = { +struct device_operations sandybridge_gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -650,16 +650,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; - -static const unsigned short pci_device_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, - 0x0116, 0x0122, 0x0126, 0x0156, - 0x0166, 0x0162, 0x016a, 0x0152, - 0 -}; - -static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Gerrit-Change-Number: 79114 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign host bridge ops in chipset devicetree
by Felix Held (Code Review) 18 Nov '23

18 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79113?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/sandybridge: assign host bridge ops in chipset devicetree ...................................................................... nb/intel/sandybridge: assign host bridge ops in chipset devicetree Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 2 insertions(+), 14 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 5635ca6..9fb1701 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -10,7 +10,7 @@ end device domain 0 on ops sandybridge_pci_domain_ops - device pci 00.0 alias host_bridge on end # host bridge + device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end device pci 01.0 alias peg10 off end # PEG10 device pci 01.1 alias peg11 off end # PEG11 device pci 01.2 alias peg12 off end # PEG12 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 9511cc3..6b89710 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -390,7 +390,7 @@ set_above_4g_pci(dev); } -static struct device_operations mc_ops = { +struct device_operations sandybridge_host_bridge_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -399,18 +399,6 @@ .acpi_fill_ssdt = mc_gen_ssdt, }; -static const unsigned short pci_device_ids[] = { - 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ - 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ - 0 -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; - struct device_operations sandybridge_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/79113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Gerrit-Change-Number: 79113 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/asus/p8z77-m_pro: Drop useless early init code
by Keith Hui (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Angel Pons, Paul Menzel, Vlado Cibic. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73693?usp=email ) Change subject: mb/asus/p8z77-m_pro: Drop useless early init code ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > The board could probably select the `SUPERIO_NUVOTON_*_COM_A` option in Kconfig, at least serial out […] I need to do this for my p8z77-m too, probably the entire family. I can include that in my own patch but I can't test anything other than what I have. -- To view, visit https://review.coreboot.org/c/coreboot/+/73693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304fc1610740375b59121b6b8784122440795838 Gerrit-Change-Number: 73693 Gerrit-PatchSet: 8 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vlado Cibic Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Vlado Cibic Gerrit-Comment-Date: Sat, 18 Nov 2023 15:35:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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