coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/puff/var/*: Set LAN device type back to pci
by Matt DeVillier (Code Review) 20 Nov '23

20 Nov '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79149?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/puff/var/*: Set LAN device type back to pci ...................................................................... mb/google/puff/var/*: Set LAN device type back to pci This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb 10 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/79149/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Gerrit-Change-Number: 79149 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Fix ACPI S3 suspend
by Keith Hui (Code Review) 20 Nov '23

20 Nov '23

Attention is currently required from: Kevin Keijzer. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78205?usp=email ) Change subject: mb/asus/p8z77-m: Fix ACPI S3 suspend ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Tested this on a P8Z77-M. […] Kevin can you test again with latest origin/main plus this patch? It's still broken for me even with, regardless I set this bit in early init or devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/78205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Gerrit-Change-Number: 78205 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Comment-Date: Mon, 20 Nov 2023 00:26:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/asus/p8z77-m[_pro]: Properly configure early serial
by Keith Hui (Code Review) 20 Nov '23

20 Nov '23

Attention is currently required from: Angel Pons, Patrick Rudolph, Paul Menzel, Vlado Cibic. Hello Angel Pons, Patrick Rudolph, Vlado Cibic, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73693?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Patrick Rudolph Change subject: mb/asus/p8z77-m[_pro]: Properly configure early serial ...................................................................... mb/asus/p8z77-m[_pro]: Properly configure early serial p8z77-m was not producing serial output until well into ramstage. p8z77-m_pro has incomplete early init code meant to configure serial port A but didn't actually do anything. To address both issues, select SUPERIO_NUVOTON_COMMON_COM_A to tell nuvoton_enable_serial() to route serial port A signals to the outside, not GPIO8x. Drop the broken early init code from p8z77-m_pro. I'll also take this chance to revise its #includes based on include-what-you-use results. TEST=Full native raminit debug log received over serial by minicom. Change-Id: I304fc1610740375b59121b6b8784122440795838 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c 2 files changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/73693/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/73693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304fc1610740375b59121b6b8784122440795838 Gerrit-Change-Number: 73693 Gerrit-PatchSet: 9 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vlado Cibic Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Vlado Cibic Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Move EINJ code to vendorcode/ocp
by David Hendricks (Code Review) 20 Nov '23

20 Nov '23

Attention is currently required from: Arthur Heymans, Jonathan Zhang, Lance Zhao, Martin L Roth, Rocky Phagura, Tim Wawrzynczak. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77416?usp=email ) Change subject: acpi: Move EINJ code to vendorcode/ocp ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77416/comment/d5b56a48_f4abd0f2 : PS3, Line 7: acpi: Move EINJ code to vendorcode/ocp > They *could* stay, but there's no reason to keep them if we're moving everything else out. […] Breaking apart the header seems fine IMO, but I wouldn't consider things written from the ACPI spec to be akin to "random tables". How about moving `acpi_einj_smi_t` out, but keep the #defines and tables like `acpi_einj_action_table_t` in `include/acpi/`? -- To view, visit https://review.coreboot.org/c/coreboot/+/77416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e91b0730cf3fcef0c54c513181c973bfe18bacf Gerrit-Change-Number: 77416 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 20 Nov 2023 00:05:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/byra/var/*: Set LAN device type back to pci
by Matt DeVillier (Code Review) 19 Nov '23

19 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79150?usp=email ) Change subject: mb/google/byra/var/*: Set LAN device type back to pci ...................................................................... mb/google/byra/var/*: Set LAN device type back to pci This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/aurash/overridetree.cb M src/mainboard/google/brya/variants/brask/overridetree.cb M src/mainboard/google/brya/variants/constitution/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/gladios/overridetree.cb M src/mainboard/google/brya/variants/kinox/overridetree.cb M src/mainboard/google/brya/variants/kuldax/overridetree.cb M src/mainboard/google/brya/variants/lisbon/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb M src/mainboard/google/brya/variants/osiris/overridetree.cb 11 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/79150/1 diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 7bea703..159c32d 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -232,7 +232,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end #RTL8111H Ethernet NIC device ref pcie_rp4 off end diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index 09f7c66..2b9ebfe 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -163,7 +163,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device generic 0 on end + device pci 00.0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -171,7 +171,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end #pcie_rp 8 Empty diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index a8393b4..995f20c 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -78,7 +78,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8125 Ethernet NIC device ref pcie4_0 on diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 41d5022..c6083f1 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -181,7 +181,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8125 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index d198530..b3af7c1 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -230,7 +230,7 @@ register "customized_leds" = "0x0843" register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" - device generic 0 on end + device pci 00.0 on end end end #PCIE7 RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 0aa0e75..6a21f2a 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 71d0e27..567f878 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -278,7 +278,7 @@ register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index 6db03ac..a6adecf 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -207,7 +207,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8125 and RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 0aa0e75..6a21f2a 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 5397463..e636540 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -164,7 +164,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device generic 0 on end + device pci 00.0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -172,7 +172,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 7ff5925..e8b78ca 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -287,7 +287,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device generic 0 on end + device pci 00.0 on end end # Enable PCIE 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/79150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Gerrit-Change-Number: 79150 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/puff/var/*: Set LAN device type back to pci
by Matt DeVillier (Code Review) 19 Nov '23

19 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79149?usp=email ) Change subject: mb/google/puff/var/*: Set LAN device type back to pci ...................................................................... mb/google/puff/var/*: Set LAN device type back to pci This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/puff/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/79149/1 diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index b7a9674..6a32bdc 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ device pci 1d.5 on chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" - device generic 0 on end + device pci 00.0 on end end register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) -- To view, visit https://review.coreboot.org/c/coreboot/+/79149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Gerrit-Change-Number: 79149 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/x86: Support SMBASE relocation-only use-case
by Benjamin Doron (Code Review) 19 Nov '23

19 Nov '23

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Martin L Roth, Matt DeVillier, Matt DeVillier, Maulik Vaghela, Raul Rangel, Subrata Banik, Tarun, Tarun Tuli, ron minnich. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70376?usp=email ) Change subject: cpu/x86: Support SMBASE relocation-only use-case ...................................................................... Patch Set 7: (1 comment) File src/southbridge/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/70376/comment/10db7338_3237e1d9 : PS7, Line 93: HAVE_SMI_HANDLER > Ah, because from memory, this would leave SPI, etc. […] Hmm, this omits `southbridge_finalize_all()`. Not great. i82801gx locks SPI using ramstage, it's the others that perform more extensive locking in SMM. Optimally, this could be performed in ramstage, I may end up looking into that. There's an alternative, sort of a workaround: make this use case depend on 'not SOUTHBRIDGE_INTEL_COMMON' This brings up the bigger issue of APM_CNT_FINALIZE. For the platforms we expect to actually enable this, SOC_INTEL_COMMON, most lockdown is complete: it omits mb/google/dedede EC's lock, `soc_lock_gpios()` and disabling HECI on some SoCs. -- To view, visit https://review.coreboot.org/c/coreboot/+/70376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec96bab19cdcf80622756f02a3dae49b42036c8d Gerrit-Change-Number: 70376 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 19 Nov 2023 17:54:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Documentation/releases: Add 24.02 release notes template
by Martin L Roth (Code Review) 19 Nov '23

19 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79073?usp=email ) Change subject: Documentation/releases: Add 24.02 release notes template ...................................................................... Documentation/releases: Add 24.02 release notes template In preparation for the upcoming release, add the template for the 24.02 release and update index.md. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I694142c31ba684e7b94640d55302b2440e25619a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79073 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A Documentation/releases/coreboot-24.02-relnotes.md M Documentation/releases/index.md 2 files changed, 101 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md new file mode 100644 index 0000000..40350ec --- /dev/null +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -0,0 +1,99 @@ +Upcoming release - coreboot 24.02 +======================================================================== + +The 24.02 release is scheduled for Mid February, 2024 + + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. +* Note that all changes before the release are done are marked upcoming. + A final version of the notes are done after the release. + +### Release number format update + +The previous release was the last to use the incrementing 4.xx release +name scheme. For this and future releases, coreboot has switched to a +Year.Month.Sub-version naming scheme. As such, the next release, +scheduled for May of 2024 will be numbered 24.05, with the sub-version +of 00 implied. If we need to do a fix or incremental release, we’ll +append the values .01, .02 and so on to the initial release value. + + +Significant or interesting changes +---------------------------------- + +* Add changes that need a full description here + +* This section should have full descriptions and can or should have + a link to the referenced commits. + + + +Additional coreboot changes +--------------------------- + +The following are changes across a number of patches, or changes worth +noting, but not needing a full description. + +* Changes that only need a line or two of description go here. + + +Changes to external resources +----------------------------- + +### Toolchain updates + + +### Git submodule pointers + + +### External payloads + + +Platform Updates +---------------- + +### Added mainboards: +* To be filled in immediately before the release by the release team + + +### Removed Mainboards +* To be filled in immediately before the release by the release team + + +### Updated SoCs +* To be filled in immediately before the release by the release team + + +Plans to move platform support to a branch +------------------------------------------ +* To be filled in immediately before the release by the release team + + +Statistics from the 4.22 to the 24.02 release +-------------------------------------------- +* To be filled in immediately before the release by the release team + + + +Significant Known and Open Issues +--------------------------------- + +Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +* To be filled in immediately before the release by the release team + + + +coreboot Links and Contact Information +-------------------------------------- + +* Main Web site: https://www.coreboot.org +* Downloads: https://coreboot.org/downloads.html +* Source control: https://review.coreboot.org +* Documentation: https://doc.coreboot.org +* Issue tracker: https://ticket.coreboot.org/projects/coreboot +* Donations: https://coreboot.org/donate.html diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index d23b03a..74968d3 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -3,7 +3,7 @@ ## Upcoming release Please add to the release notes as changes are added: -* [4.22 - November 2023](coreboot-4.22-relnotes.md) +* [24.02 - February 2024](coreboot-24.02-relnotes.md) The [checklist] contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -15,6 +15,7 @@ ## Previous releases +* [4.22 - November 2023](coreboot-4.22-relnotes.md) * [4.21 - August 2023](coreboot-4.21-relnotes.md) * [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md) * [4.19 - January 2023](coreboot-4.19-relnotes.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/79073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I694142c31ba684e7b94640d55302b2440e25619a Gerrit-Change-Number: 79073 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 19 Nov '23

19 Nov '23

Attention is currently required from: Angel Pons, Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 22: (4 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/6b8bc89c_3e51356e : PS17, Line 12: typedef > Plus, if a function's signature is too long, you can spread the parameter list of a function over several lines. If you have too many parameters, consider passing a pointer to a struct instead. That's something I usually try to avoid. I have removed the typedefs now. https://review.coreboot.org/c/coreboot/+/78071/comment/789dc5a5_29b922c9 : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > Looks like https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Programming_… says that the "processor hierarchy node structure (Type 0) [...] can be used to describe a single processor or a group". Looks like the code doesn't make use of this yet? If they mean clusters, current code allows you to create clusters. See https://review.coreboot.org/c/coreboot/+/79108/3 Otherwise, not sure what they mean by group. > There's a few things to keep in mind: - The processor info needs to match that of MADT, not sure if MADT accounts for processor groups. - It is assumed that whoever defines acpi_get_pptt_topology() can figure out how to group the processors better than common code (e.g. soc/rockchip/rk3399 knows the chip has 2x Cortex-A72 and 4x Cortex-A53, common code doesn't). Agreed. > If one processor has L1->L2->0 and another processor only has L2->0 (where 0 means NULL and L2 is the exact same data), one could try to reuse parts of the first processor's L1->L2-0 data for the second processor. This can also be done by comparing pointers and will work provided that acpi_get_pptt_topology() also reuses said pointers. Assuming both of these processors are on the same topology level, then yes, one can reuse the already generated `L2->0` chain. That is also what the current code is doing. It saves previously generated cache entries (per topology level) in order to reuse them later for another processor, if needed. File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78071/comment/c222d388_e3060fbf : PS21, Line 1405: PPTT_PROCESSOR_FLAG_* > Macros do not exist Done https://review.coreboot.org/c/coreboot/+/78071/comment/f5370641_4ed9d9bc : PS21, Line 1416: PPTT_CACHE_FLAG_* > Macros do not exist Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 22 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 19 Nov 2023 17:29:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add PPTT support
by David Milosevic (Code Review) 19 Nov '23

19 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78071?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add PPTT support ...................................................................... acpi: Add PPTT support This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/acpi.c A src/acpi/acpi_pptt.c M src/include/acpi/acpi.h 5 files changed, 324 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78071/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 22 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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